INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) :=
x"00000000_00000000_00000000_00000000" &
x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_000090FF_00000000" &
+ x"00000000_00000000_00007077_00000000" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
--Timeouts 88-8B
if reg_STROBES(8) = '1' then
HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' then
+ elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then
HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or HC_STAT_REGS(8*32+31 downto 8*32);
end if;
if reg_STROBES(9) = '1' then
HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' then
+ elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then
HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or HC_STAT_REGS(9*32+31 downto 9*32);
end if;
- if reg_STROBES(10) = '1' then
+-- if reg_STROBES(10) = '1' then
HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' then
- HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or HC_STAT_REGS(10*32+31 downto 10*32);
- end if;
+-- elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then
+-- HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or HC_STAT_REGS(10*32+31 downto 10*32);
+-- end if;
if reg_STROBES(11) = '1' then
HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' then
+ elsif combined_resync = '0' and reset_i = '0' and timer_ms_tick = '1' then
HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or HC_STAT_REGS(11*32+31 downto 11*32);
end if;
else
HC_STAT_REGS(13*32+31 downto 13*32) <= HC_STAT_ack_waiting(1*32+31 downto 1*32) or HC_STAT_REGS(13*32+31 downto 13*32);
end if;
- if reg_STROBES(14) = '1' then
+-- if reg_STROBES(14) = '1' then
HC_STAT_REGS(14*32+31 downto 14*32) <= (others => '0');
- else
- HC_STAT_REGS(14*32+31 downto 14*32) <= HC_STAT_ack_waiting(2*32+31 downto 2*32) or HC_STAT_REGS(14*32+31 downto 14*32);
- end if;
+-- else
+-- HC_STAT_REGS(14*32+31 downto 14*32) <= HC_STAT_ack_waiting(2*32+31 downto 2*32) or HC_STAT_REGS(14*32+31 downto 14*32);
+-- end if;
if reg_STROBES(15) = '1' then
HC_STAT_REGS(15*32+31 downto 15*32) <= (others => '0');
else
--LSM packet timeout A6
if reg_STROBES(38) = '1' then
HC_STAT_REGS(38*32+31 downto 38*32) <= (others => '0');
- else
+ elsif reset_i = '0' then
for i in 0 to MII_NUMBER-1 loop
HC_STAT_REGS(38*32+i) <= HC_STAT_REGS(38*32+i) or (MED_STAT_OP(i*16+12));
end loop;
signal REPLY_POOL_next_read : std_logic;
signal comb_REPLY_POOL_next_read : std_logic;
-
+ signal reg_stat_timeout : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_point_lock, next_point_lock : std_logic;
signal comb_REPLY_muxed_DATAREADY : std_logic;
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or got_trm(i) = '1'
- or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then
+ or reset_i = '1' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then
connection_timed_out(i) <= '1';
-- elsif timer_ms_tick = '1' and INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1' then
-- timeout_counter(i) <= timeout_counter(i) + to_unsigned(2,2);
- elsif timer_ms_tick = '1' and ((REPLY_POOL_next_read = '1' and got_trm(i) = '0')
+ elsif timer_ms_tick = '1' and ((REPLY_POOL_next_read = '1') -- and got_trm(i) = '0'
or (INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1')) then
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
end if;
----------------------------------
--Debugging
----------------------------------
-
- STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= connection_timed_out;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if timer_ms_tick = '1' or reset_i = '1' then
+ reg_stat_timeout <= (others => '0');
+ else
+ reg_stat_timeout <= reg_stat_timeout or connection_timed_out;
+ end if;
+ end if;
+ end process;
+
+ STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= reg_stat_timeout;
STAT_TIMEOUT(31 downto POINT_NUMBER) <= (others => '0');
STAT(0) <= got_trm(0);