small fixes, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 1f5f6c5674cc8e8798001cf4509f6ea38e24d937..5ae30a9b94d41bf8d53f1ac11e01da682db6fa51 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -106,6 +106,11 @@ architecture arch of generic_flash_ctrl is
   signal reg_LOC_ADDR_OUT  : std_logic_vector(7 downto 0);
   signal reg_LOC_WRITE_OUT : std_logic;
   signal reg_LOC_READ_OUT  : std_logic;
+
+  signal reg_SPI_DATA_IN : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
+  signal reg_SPI_ADDR_IN : std_logic_vector(7 downto 0);
+  signal reg_SPI_READ_IN : std_logic;
+  signal reg_SPI_WRITE_IN : std_logic;
   
   signal flashram_addr_i : std_logic_vector(3 downto 0);
   signal flashram_cen_i  : std_logic;
@@ -243,6 +248,15 @@ begin
   ram_data_o <= raw_ram_data_o;
 end process;
 
+--reg_SPI : process begin
+--  wait until rising_edge(clk_l);
+
+--  reg_SPI_DATA_IN <= SPI_DATA_IN;
+--  reg_SPI_ADDR_IN <= SPI_ADDR_IN;
+--  reg_SPI_WRITE_IN <= SPI_WRITE_IN;
+--  reg_SPI_READ_IN <= SPI_READ_IN;
+--end process;
+  
 PROC_SELECTOR : process begin
   wait until rising_edge(clk_l);
 
@@ -290,7 +304,7 @@ PROC_SELECTOR : process begin
       testreg <= SPI_DATA_IN;
     elsif (SPI_ADDR_IN(7 downto 0) = x"51") then
       flash_command_register <= SPI_DATA_IN(3 downto 1);
-    elsif (SPI_ADDR_IN(7 downto 0) = x"50") then
+    elsif (SPI_ADDR_IN(7 downto 0) = x"50" and spi_flash_go = '0') then
       reg_LOC_WRITE_OUT <= '0';
       if (flash_mode = '0') then
         spi_flash_command <= SPI_DATA_IN(15 downto 13);
@@ -327,18 +341,20 @@ PROC_SELECTOR : process begin
     end if;
   elsif (out_delay = "010") then
     reg_LOC_READ_OUT  <= '0';
+    reg_SPI_READY_OUT  <= '0';
     out_delay <= "011";
     if (memreg(1) = '1') then
       -- at least 24 bit burst
       spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); --prepare nibble3
     end if;
   elsif (out_delay = "011") then
+    reg_LOC_READ_OUT  <= '0';
     if (memreg(0) = '0') then
-      out_delay <= "000";
+      out_delay <= "111";
       reg_SPI_DATA_OUT(15 downto 0) <= flash_busy & flash_err & "000000" & ram_data_o; -- write nibble1
       reg_SPI_READY_OUT <= '1';
     else
-      reg_LOC_READ_OUT  <= '0';
+      reg_SPI_READY_OUT <= '0';
       if (memreg(4) = '1') then
         reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) <= ram_data_o;
       else
@@ -357,7 +373,7 @@ PROC_SELECTOR : process begin
     reg_SPI_READY_OUT <= '0';
     out_delay <= "101";
     if (memreg(1) = '0' or DATA_BUS_WIDTH < 24) then
-      out_delay <= "000";
+      out_delay <= "111";
       reg_SPI_READY_OUT <= '1';
     end if;
   elsif (out_delay = "101") then
@@ -372,7 +388,7 @@ PROC_SELECTOR : process begin
     reg_SPI_READY_OUT <= '0';
     out_delay <= "110";    
     if (DATA_BUS_WIDTH < 32) then
-      out_delay <= "000";
+      out_delay <= "111";
       reg_SPI_READY_OUT <= '1';
     end if;
   elsif (out_delay = "110") then
@@ -385,7 +401,7 @@ PROC_SELECTOR : process begin
         reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);
       end if;
     end if;
-    out_delay <= "000";
+    out_delay <= "111";
   else
     out_delay <= "000";
   end if;
@@ -399,7 +415,7 @@ PROC_SELECTOR : process begin
   end if;
   
   if (SPI_READ_IN = '1') then    
-    if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000") then
+    if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000" and out_delay = "000") then
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
       out_delay <= "001";
       reg_LOC_READ_OUT  <= '0';