COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
READ_EN_IN : in std_logic; -- read en signal
FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out
- FIFO_WCNT_OUT : out unsigned(7 downto 0);
+ FIFO_WCNT_OUT : out unsigned(7 downto 0); -- fifo write counter out
FIFO_EMPTY_OUT : out std_logic; -- fifo empty signal
FIFO_FULL_OUT : out std_logic; -- fifo full signal
FIFO_ALMOST_FULL_OUT : out std_logic;
--
--- FIFO_WR_OUT : out std_logic;
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic);
hit_detect_reg <= hit_detect_i when rising_edge(CLK_200);
hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200);
coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200);
--- encoder_start_i <= hit_detect_reg;
encoder_start_i <= hit_detect_i;
ENCODER_START_OUT <= encoder_start_i;
end if;
end process FifoWriteSignal;
---FIFO_WR_OUT <= fifo_wr_en_i;
ENCODER_FINISHED_OUT <= encoder_finished_i;
RegisterOutputs : process (CLK_100)
end if;
end if;
end process RegisterOutputs;
-
end Channel_200;
-- File : Reference_channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-09-04
--- Last update: 2013-03-04
+-- Last update: 2013-03-05
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal encoder_debug_i : std_logic_vector(31 downto 0);
-- fifo
- signal fifo_data_out_i : std_logic_vector(35 downto 0);
signal fifo_data_in_i : std_logic_vector(35 downto 0);
+ signal fifo_data_out_i : std_logic_vector(35 downto 0);
signal fifo_wcnt_i : std_logic_vector(7 downto 0);
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
hit_detect_reg <= hit_detect_i when rising_edge(CLK_200);
hit_detect_2reg <= hit_detect_reg when rising_edge(CLK_200);
coarse_cntr_reg <= COARSE_COUNTER_IN when rising_edge(CLK_200);
--- encoder_start_i <= hit_detect_reg;
encoder_start_i <= hit_detect_i;
TimeStampCapture : process (CLK_200)
else
fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
end if;
--- fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder
fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge
fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp
coarse_cntr_overflow_release <= '0';