ADC_DATA_OUT : out std_logic_vector(11 downto 0);
NEW_DATA_OUT : out std_logic;
- DATA_DELAY_VALUE_OUT : out unsigned(6 downto 0);
+ FIFO_DELAY_IN : in std_logic_vector(6 downto 0);
-- Slave bus
SLV_READ_IN : in std_logic;
DEBUG_OUT(6) <= fifo_read_enable;
DEBUG_OUT(7) <= fifo_data_valid;
DEBUG_OUT(8) <= new_data_o;
- DEBUG_OUT(15 downto 9) <= nx_frame_o(6 downto 0);
+ DEBUG_OUT(15 downto 9) <= fifo_delay;
-----------------------------------------------------------------------------
-- FIFO Delay Handler
end if;
end if;
end process PROC_NX_FIFO_READ;
-
+
+ PROC_FIFO_DELAY: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ fifo_delay <= "0000001";
+ fifo_delay_reset <= '0';
+ else
+ fifo_delay_reset <= '0';
+ if (fifo_delay /= FIFO_DELAY_IN) then
+ if (unsigned(FIFO_DELAY_IN) >= 1 and
+ unsigned(FIFO_DELAY_IN) <= 120) then
+ fifo_delay <= FIFO_DELAY_IN;
+ fifo_delay_reset <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process PROC_FIFO_DELAY;
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- fifo_delay <= "0001010";
- fifo_delay_reset <= '0';
else
slv_data_o <= (others => '0');
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- fifo_delay_reset <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
end case;
elsif (SLV_WRITE_IN = '1') then
- case SLV_ADDR_IN is
- when x"0000" =>
- if (unsigned(SLV_DATA_IN(6 downto 0)) >= 1 and
- unsigned(SLV_DATA_IN(6 downto 0)) <= 120) then
- fifo_delay <= SLV_DATA_IN(6 downto 0);
- fifo_delay_reset <= '1';
- end if;
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
-
- end case;
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
else
slv_ack_o <= '0';
end if;
NX_FRAME_OUT <= nx_frame_o;
ADC_DATA_OUT <= adc_data_o;
NEW_DATA_OUT <= new_data_o;
- DATA_DELAY_VALUE_OUT <= unsigned(fifo_delay);
SLV_DATA_OUT <= slv_data_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
signal adc_new_data : std_logic;
signal adc_new_data_ctr : unsigned(3 downto 0);
+ -- ADC TEST INPUT DATA
+ signal adc_input_error_enable : std_logic;
+ signal adc_input_error_ctr : unsigned(15 downto 0);
+
+
-- Data Output Handler
type STATES is (IDLE,
WAIT_ADC,
begin
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;
- DEBUG_OUT(2) <= TRIGGER_IN;
-
PROC_DEBUG_MULT: process(debug_adc,
adc_data,
adc_data_valid,
begin
case debug_adc is
when "01" =>
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;
+ DEBUG_OUT(2) <= TRIGGER_IN;
DEBUG_OUT(3) <= adc_data_valid;
DEBUG_OUT(15 downto 4) <= adc_data;
when "10" =>
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;
+ DEBUG_OUT(2) <= TRIGGER_IN;
DEBUG_OUT(3) <= adc_data_valid;
DEBUG_OUT(15 downto 4) <= test_adc_data;
when "11" =>
+ DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN;
+ DEBUG_OUT(1) <= CLK_IN;
+ DEBUG_OUT(2) <= TRIGGER_IN;
DEBUG_OUT(3) <= adc_clk_ok;
DEBUG_OUT(4) <= adc_clk_ok_last;
DEBUG_OUT(5) <= adc_clk_skip;
- DEBUG_OUT(6) <= adc_reset_s;
- DEBUG_OUT(7) <= adc_reset;
- DEBUG_OUT(8) <= '0';
- DEBUG_OUT(9) <= nx_new_frame;
- DEBUG_OUT(15 downto 10) <= adc_reset_ctr(5 downto 0) ;
+ DEBUG_OUT(6) <= adc_reset_r;
+ DEBUG_OUT(7) <= adc_reset_l;
+ DEBUG_OUT(8) <= adc_reset_s;
+ DEBUG_OUT(9) <= adc_reset;
+ DEBUG_OUT(10) <= nx_new_frame;
+ DEBUG_OUT(15 downto 11) <= adc_reset_ctr(4 downto 0) ;
when others =>
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;
+ DEBUG_OUT(2) <= TRIGGER_IN;
DEBUG_OUT(3) <= nx_fifo_full;
DEBUG_OUT(4) <= nx_fifo_write_enable;
DEBUG_OUT(5) <= nx_fifo_empty;
DEBUG => open
);
- adc_reset <= adc_reset_l or RESET_IN;
+ adc_reset <= adc_reset_s or adc_reset_l or RESET_IN;
pulse_to_level_1: pulse_to_level
generic map (
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
if (RESET_IN = '1') then
- parity_error <= '0';
+ parity_error <= '0';
else
- parity_error <= '0';
+ parity_error <= '0';
if (nx_new_frame = '1' and nx_frame_synced = '1') then
-- Timestamp Bit #6 is excluded (funny nxyter-bug)
parity_bits := nx_frame_word(31) &
begin
if (rising_edge(CLK_IN) ) then
if (RESET_IN = '1' or reset_parity_error_ctr = '1') then
- parity_error_counter <= (others => '0');
+ parity_error_counter <= (others => '0');
else
if (parity_error_ctr_inc = '1') then
parity_error_counter <= parity_error_counter + 1;
end if;
end if;
end process PROC_ADC_DATA_READ;
-
+
+ PROC_ADC_TEST_INPUT_DATA: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ adc_input_error_ctr <= (others => '0');
+ else
+ if (adc_input_error_enable = '1') then
+ if (adc_new_data = '1' and
+ adc_data_t /= x"fff" and
+ adc_data_t /= x"000") then
+ adc_input_error_ctr <= adc_input_error_ctr + 1;
+ end if;
+ else
+ adc_input_error_ctr <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process PROC_ADC_TEST_INPUT_DATA;
+
-----------------------------------------------------------------------------
-- Output handler
-----------------------------------------------------------------------------
begin
if (rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- reset_resync_ctr <= '0';
- reset_parity_error_ctr <= '0';
- fifo_reset_r <= '0';
- adc_clk_delay <= "111";
- adc_reset_r <= '0';
- debug_adc <= (others => '0');
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ reset_resync_ctr <= '0';
+ reset_parity_error_ctr <= '0';
+ fifo_reset_r <= '0';
+ adc_clk_delay <= "111";
+ adc_reset_r <= '0';
+ debug_adc <= (others => '0');
+ adc_input_error_enable <= '0';
else
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- reset_resync_ctr <= '0';
- reset_parity_error_ctr <= '0';
- fifo_reset_r <= '0';
- adc_reset_r <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ reset_resync_ctr <= '0';
+ reset_parity_error_ctr <= '0';
+ fifo_reset_r <= '0';
+ adc_reset_r <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o <= nx_timestamp_t;
- slv_ack_o <= '1';
+ slv_data_out_o <= nx_timestamp_t;
+ slv_ack_o <= '1';
when x"0001" =>
- slv_data_out_o(0) <= nx_fifo_full;
- slv_data_out_o(1) <= nx_fifo_empty;
- slv_data_out_o(2) <= '0';
- slv_data_out_o(3) <= '0';
- slv_data_out_o(4) <= nx_fifo_data_valid;
- slv_data_out_o(5) <= adc_new_data;
- slv_data_out_o(29 downto 5) <= (others => '0');
- slv_data_out_o(30) <= '0';
- slv_data_out_o(31) <= reg_nx_frame_synced;
- slv_ack_o <= '1';
+ slv_data_out_o(0) <= nx_fifo_full;
+ slv_data_out_o(1) <= nx_fifo_empty;
+ slv_data_out_o(2) <= '0';
+ slv_data_out_o(3) <= '0';
+ slv_data_out_o(4) <= nx_fifo_data_valid;
+ slv_data_out_o(5) <= adc_new_data;
+ slv_data_out_o(29 downto 5) <= (others => '0');
+ slv_data_out_o(30) <= '0';
+ slv_data_out_o(31) <= reg_nx_frame_synced;
+ slv_ack_o <= '1';
when x"0002" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(resync_counter);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0) <= std_logic_vector(resync_counter);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"0003" =>
- slv_data_out_o(11 downto 0) <=
+ slv_data_out_o(11 downto 0) <=
std_logic_vector(parity_error_counter);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"0005" =>
case adc_clk_delay is
when "111" => slv_data_out_o(2 downto 0) <= "111";
end case;
- slv_data_out_o(31 downto 3) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_ack_o <= '1';
when x"0006" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"0007" =>
- slv_data_out_o(1 downto 0) <= debug_adc;
- slv_data_out_o(31 downto 2) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(1 downto 0) <= debug_adc;
+ slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_ack_o <= '1';
when x"0008" =>
- slv_data_out_o(11 downto 0) <= adc_data_t;
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_data_out_o(11 downto 0) <= adc_data_t;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0009" =>
+ slv_data_out_o(0) <= adc_input_error_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000a" =>
+ slv_data_out_o(15 downto 0) <= adc_input_error_ctr;
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
+ slv_unknown_addr_o <= '1';
end case;
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0001" =>
- adc_reset_r <= '1';
- slv_ack_o <= '1';
+ adc_reset_r <= '1';
+ slv_ack_o <= '1';
when x"0002" =>
- reset_resync_ctr <= '1';
- slv_ack_o <= '1';
+ reset_resync_ctr <= '1';
+ slv_ack_o <= '1';
when x"0003" =>
- reset_parity_error_ctr <= '1';
- slv_ack_o <= '1';
+ reset_parity_error_ctr <= '1';
+ slv_ack_o <= '1';
when x"0005" =>
if (SLV_DATA_IN < x"0000_0008") then
when "111" => adc_clk_delay <= "111";
end case;
end if;
- slv_ack_o <= '1';
+ slv_ack_o <= '1';
when x"0007" =>
- debug_adc <= SLV_DATA_IN(1 downto 0);
- slv_ack_o <= '1';
-
+ debug_adc <= SLV_DATA_IN(1 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0009" =>
+ adc_input_error_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
+ slv_unknown_addr_o <= '1';
+
end case;
end if;
end if;
when "1000" =>
---- Check Overflow
if ((status_bits(0) = '1') and (clear_counters = '0')) then
- overflow_ctr <= overflow_ctr + 1;
+ overflow_ctr <= overflow_ctr + 1;
end if;
---- Check Parity
if ((parity_bit /= parity) and (clear_counters = '0')) then
- timestamp_status_o(0) <= '1';
- parity_error_ctr <= parity_error_ctr + 1;
+ timestamp_status_o(2) <= '1';
+ parity_error_ctr <= parity_error_ctr + 1;
+ else
+ timestamp_status_o(2) <= '0';
end if;
-- Check PileUp
if ((status_bits(1) = '1') and (clear_counters = '0')) then
- pileup_ctr <= pileup_ctr + 1;
+ pileup_ctr <= pileup_ctr + 1;
end if;
-- Take Timestamp
timestamp_o <= nx_timestamp;
channel_o <= nx_channel_id;
- timestamp_status_o(2 downto 1) <= status_bits;
+ timestamp_status_o(1 downto 0) <= status_bits;
adc_data_o <= adc_data;
data_valid_o <= '1';
if (adc_data = x"aff") then
- invalid_adc <= '1';
+ invalid_adc <= '1';
end if;
- nx_token_return_o <= '0';
- nx_nomore_data_o <= '0';
- trigger_rate_inc <= '1';
+ nx_token_return_o <= '0';
+ nx_nomore_data_o <= '0';
+ trigger_rate_inc <= '1';
-- Token return and nomore_data
when "0000" =>
- nx_token_return_o <= '1';
- nx_nomore_data_o <= nx_token_return_o;
+ nx_token_return_o <= '1';
+ nx_nomore_data_o <= nx_token_return_o;
when others =>
-- Invalid frame, not empty, discard timestamp
if (clear_counters = '0') then
- invalid_frame_ctr <= invalid_frame_ctr + 1;
+ invalid_frame_ctr <= invalid_frame_ctr + 1;
end if;
- nx_token_return_o <= '0';
- nx_nomore_data_o <= '0';
+ nx_token_return_o <= '0';
+ nx_nomore_data_o <= '0';
end case;
- frame_rate_inc <= '1';
+ frame_rate_inc <= '1';
else
- nx_token_return_o <= nx_token_return_o;
- nx_nomore_data_o <= nx_nomore_data_o;
+ nx_token_return_o <= nx_token_return_o;
+ nx_nomore_data_o <= nx_nomore_data_o;
end if;
-- Reset Counters
if (clear_counters = '1') then
- invalid_frame_ctr <= (others => '0');
- overflow_ctr <= (others => '0');
- pileup_ctr <= (others => '0');
- parity_error_ctr <= (others => '0');
+ invalid_frame_ctr <= (others => '0');
+ overflow_ctr <= (others => '0');
+ pileup_ctr <= (others => '0');
+ parity_error_ctr <= (others => '0');
end if;
end if;
end if;
--LVL1 trigger
LVL1_TRG_DATA_VALID_IN : in std_logic; -- timing trigger valid, later
- LVL1_VALID_TIMING_TRG_IN : in std_logic; -- timing trigger synced
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- timing trigger raw
- LVL1_INVALID_TRG_IN : in std_logic; -- ???
+ LVL1_VALID_TIMING_TRG_IN : in std_logic; -- normal read-out trigger with
+ -- reference time
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- calibration trigger w/o
+ -- reference time
+ LVL1_INVALID_TRG_IN : in std_logic; --
LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_REF_IN : in unsigned(11 downto 0);
- DATA_DELAY_VALUE_IN : in unsigned(6 downto 0);
+ DATA_FIFO_DELAY_OUT : out std_logic_vector(6 downto 0);
-- Outputs
DATA_OUT : out std_logic_vector(31 downto 0);
signal wait_timer_reset : std_logic;
signal event_counter : unsigned(9 downto 0);
- signal readout_mode : std_logic_vector(3 downto 0);
+ signal readout_mode : std_logic_vector(2 downto 0);
signal timestamp_ref : unsigned(11 downto 0);
-- Timer
signal histogram_bin_o : std_logic_vector(6 downto 0);
signal histogram_adc_o : std_logic_vector(11 downto 0);
+ -- Data FIFO Delay
+ signal data_fifo_delay_o : std_logic_vector(6 downto 0);
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal readout_mode_r : std_logic_vector(3 downto 0);
- signal trigger_window_width : unsigned(11 downto 0);
- signal trigger_window_delay : unsigned(11 downto 0);
+ signal readout_mode_r : std_logic_vector(2 downto 0);
+ signal trigger_window_begin : unsigned(11 downto 0);
+ signal trigger_window_end : unsigned(11 downto 0);
+ signal cts_trigger_delay : unsigned(11 downto 0);
signal readout_time_max : unsigned(11 downto 0);
-
signal window_lower_thr_r : std_logic_vector(11 downto 0);
signal window_upper_thr_r : std_logic_vector(11 downto 0);
-
+
begin
-
+
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= TRIGGER_IN;
if (DATA_CLK_IN = '1') then
if (store_to_fifo = '1') then
- ts_ref := timestamp_ref - x"010";
- window_lower_thr := trigger_window_delay;
- window_upper_thr := window_lower_thr + trigger_window_width;
+ ts_ref := timestamp_ref - cts_trigger_delay;
+ window_lower_thr := trigger_window_begin;
+ window_upper_thr := window_lower_thr + trigger_window_end;
deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref;
deltaTStore := deltaT - window_lower_thr;
window_lower_thr_r <= window_lower_thr;
window_upper_thr_r <= window_upper_thr;
-
- case readout_mode is
- when x"0" => -- RefValue + valid + window filter limit
- if (TIMESTAMP_STATUS_IN(1) = '0') then
- if (deltaT < window_lower_thr) then
- out_of_window_l <= '1';
- data_clk_o <= '0';
- -- IN LUT-Data bit setzten.
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
- elsif (deltaT > window_upper_thr) then
- out_of_window_h <= '1';
- data_clk_o <= '0';
- -- In LUT-Done Bit setzten
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_DONE;
- else
- -- IN LUT-Data bit setzten.
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
-
+ if (readout_mode(2) = '0') then
+ -- TS window filter Modes
+ if (deltaT < window_lower_thr) then
+ out_of_window_l <= '1';
+ data_clk_o <= '0';
+ -- IN LUT Data bit setzen.
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_WAIT;
+ elsif (deltaT > window_upper_thr) then
+ out_of_window_h <= '1';
+ data_clk_o <= '0';
+ -- In LUT Done Bit setzen
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_DONE;
+ else
+ -- IN LUT Data bit setzen and Take Data
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_WAIT;
+
+ case readout_mode(1 downto 0) is
+ when "00" =>
+ -- RefValue + TS window filter + ovfl valid + parity valid
+ if (TIMESTAMP_STATUS_IN(2) = '0' and
+ TIMESTAMP_STATUS_IN(0) = '0') then
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
+ end if;
+
+ when "01" =>
+ -- RefValue + TS window filter + ovfl and pileup valid
+ -- + parity valid
+ if (TIMESTAMP_STATUS_IN(2 downto 1) = "000") then
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
+ end if;
+
+ when others =>
+ -- RefValue + TS window filter + ignore status
data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
data_o(11 downto 2) <= deltaTStore(9 downto 0);
data_o(23 downto 12) <= ADC_DATA_IN;
data_o(30 downto 24) <= CHANNEL_IN;
data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
+
+ end case;
+ end if;
+ else
+ -- No TS window filter Modes
+ case readout_mode(1 downto 0) is
+ when "00" =>
+ -- RefValue + ovfl valid + parity valid
+ if (TIMESTAMP_STATUS_IN(2) = '0' and
+ TIMESTAMP_STATUS_IN(0) = '0') then
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
end if;
- end if;
-
- when x"1" => -- RefValue + valid filter + maxtime limit
- if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
- data_o(11 downto 2) <= deltaTStore(9 downto 0);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
- end if;
- when x"3" => -- RefValue + valid filter
- if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
- data_o(11 downto 2) <= deltaTStore(9 downto 0);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
- end if;
-
- when x"4" => -- RawValue + valid filter
- if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
- end if;
-
- when x"5" => -- RawValue + maxtime limit
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
-
- when others => null;
-
- end case;
+ when "01" =>
+ -- RefValue + ovfl and pileup valid
+ -- + parity valid
+ if (TIMESTAMP_STATUS_IN(2 downto 1) = "000") then
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
+ end if;
+ when others =>
+ -- RefValue + ignore status
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
+
+ end case;
+ end if;
+
+ -- Fill Histogram
+ histogram_fill_o <= '1';
+ histogram_bin_o <= CHANNEL_IN;
+ histogram_adc_o <= ADC_DATA_IN;
end if;
-
- -- Fill Histogram
- histogram_fill_o <= '1';
- histogram_bin_o <= CHANNEL_IN;
- histogram_adc_o <= ADC_DATA_IN;
+
end if;
end if;
end if;
PROC_TRIGGER_HANDLER: process(CLK_IN)
variable min_validation_time : unsigned(11 downto 0);
- variable ts_ref : unsigned(11 downto 0);
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then
ch_status_cmd_tr <= CS_NONE;
min_validation_time := x"020" +
- (trigger_window_delay / 2) +
- (trigger_window_width / 2);
+ (trigger_window_begin / 2) +
+ (trigger_window_end / 2);
case STATE is
-- 10: DEBUG
-- 11: UNDEF
case readout_mode is
- when x"0" => t_data_o(23 downto 22) <= "00";
- when x"1" => t_data_o(23 downto 22) <= "01";
+ when "000" => t_data_o(23 downto 22) <= "00";
+ when "001" => t_data_o(23 downto 22) <= "01";
+ when "100" => t_data_o(23 downto 22) <= "10";
+ when "101" => t_data_o(23 downto 22) <= "11";
when others => t_data_o(23 downto 22) <= "11";
end case;
t_data_o(31 downto 24) <= BOARD_ID(7 downto 0);
-- Check Token_Return
if (busy_time_ctr > min_validation_time) then
- if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
+ if (readout_mode(2) = '0' and NX_TOKEN_RETURN_IN = '1') then
if (token_return_ctr = '1') then
ch_status_cmd_tr <= CS_TOKEN_UPDATE;
end if;
end if;
end if;
end process PROC_CHANNEL_STATUS;
+
+ PROC_DATA_FIFO_DELAY: process(CLK_IN)
+ variable fifo_delay : unsigned(11 downto 0);
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1') then
+ data_fifo_delay_o <= "0000001";
+ else
+ fifo_delay := (cts_trigger_delay / 8) + 1;
+ if (fifo_delay >= 1 and fifo_delay <= 120) then
+ data_fifo_delay_o <= std_logic_vector(fifo_delay(6 downto 0));
+ else
+ data_fifo_delay_o <= "0000001";
+ end if;
+ end if;
+ end if;
+ end process PROC_DATA_FIFO_DELAY;
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
-- Give status info to the TRB Slow Control Channel
- PROC_FIFO_REGISTERS: process(CLK_IN)
+ PROC_SLAVE_BUS: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- readout_mode_r <= x"0";
- trigger_window_delay <= (others => '0');
- trigger_window_width <= x"020";
+ readout_mode_r <= "000";
+ trigger_window_begin <= x"000";
+ trigger_window_end <= x"040";
+ cts_trigger_delay <= x"000";
readout_time_max <= x"640";
else
slv_data_out_o <= (others => '0');
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o(3 downto 0) <= readout_mode_r;
- slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_data_out_o( 2 downto 0) <= readout_mode_r;
+ slv_data_out_o(31 downto 3) <= (others => '0');
slv_ack_o <= '1';
when x"0001" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(trigger_window_delay);
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(trigger_window_begin);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"0002" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(trigger_window_width);
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(trigger_window_end);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"0003" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(readout_time_max);
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(cts_trigger_delay);
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0004" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(busy_time_ctr);
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(readout_time_max);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"0005" =>
- slv_data_out_o(11 downto 0) <= timestamp_ref;
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(busy_time_ctr);
slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_ack_o <= '1';
when x"0006" =>
- slv_data_out_o(11 downto 0) <= window_lower_thr_r;
+ slv_data_out_o(11 downto 0) <= timestamp_ref;
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"0007" =>
- slv_data_out_o(11 downto 0) <= window_upper_thr_r;
+ slv_data_out_o(11 downto 0) <= window_lower_thr_r;
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"0008" =>
- slv_data_out_o(6 downto 0) <=
- std_logic_vector(DATA_DELAY_VALUE_IN);
- slv_data_out_o(31 downto 7) <= (others => '0');
+ slv_data_out_o(11 downto 0) <= window_upper_thr_r;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0009" =>
+ slv_data_out_o( 6 downto 0) <=
+ std_logic_vector(data_fifo_delay_o);
+ slv_data_out_o(31 downto 7) <= (others => '0');
slv_ack_o <= '1';
- when x"0009" =>
+ when x"000a" =>
slv_data_out_o <=
std_logic_vector(channel_done(31 downto 0));
slv_ack_o <= '1';
- when x"000a" =>
+ when x"000b" =>
slv_data_out_o <=
std_logic_vector(channel_done(63 downto 32));
slv_ack_o <= '1';
- when x"000b" =>
+ when x"000c" =>
slv_data_out_o <=
std_logic_vector(channel_done(95 downto 64));
slv_ack_o <= '1';
- when x"000c" =>
+ when x"000d" =>
slv_data_out_o <=
std_logic_vector(channel_done(127 downto 96));
slv_ack_o <= '1';
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- readout_mode_r <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
+ readout_mode_r <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
when x"0001" =>
- trigger_window_delay <= SLV_DATA_IN(11 downto 0);
- slv_ack_o <= '1';
+ trigger_window_begin <= SLV_DATA_IN(11 downto 0);
+ slv_ack_o <= '1';
when x"0002" =>
- trigger_window_width <=
+ trigger_window_end <=
unsigned(SLV_DATA_IN(11 downto 0));
- slv_ack_o <= '1';
-
+ slv_ack_o <= '1';
+
when x"0003" =>
- readout_time_max <=
+ if (unsigned(SLV_DATA_IN(11 downto 0)) < 960) then
+ cts_trigger_delay <=
+ unsigned(SLV_DATA_IN(11 downto 0));
+ end if;
+ slv_ack_o <= '1';
+
+ when x"0004" =>
+ readout_time_max <=
unsigned(SLV_DATA_IN(11 downto 0));
- slv_ack_o <= '1';
-
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end case;
else
- slv_ack_o <= '0';
+ slv_ack_o <= '0';
end if;
end if;
end if;
- end process PROC_FIFO_REGISTERS;
+ end process PROC_SLAVE_BUS;
-----------------------------------------------------------------------------
-- Output Signals
DATA_OUT <= data_o or t_data_o;
DATA_CLK_OUT <= data_clk_o or t_data_clk_o;
NOMORE_DATA_OUT <= nomore_data_o;
-
+ DATA_FIFO_DELAY_OUT <= data_fifo_delay_o;
+
HISTOGRAM_FILL_OUT <= histogram_fill_o;
HISTOGRAM_BIN_OUT <= histogram_bin_o;
HISTOGRAM_ADC_OUT <= histogram_adc_o;
NX_FRAME_OUT : out std_logic_vector(31 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
NEW_DATA_OUT : out std_logic;
- DATA_DELAY_VALUE_OUT : out unsigned(6 downto 0);
+ FIFO_DELAY_IN : in std_logic_vector(6 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_REF_IN : in unsigned(11 downto 0);
- DATA_DELAY_VALUE_IN : in unsigned(6 downto 0);
+ DATA_FIFO_DELAY_OUT : out std_logic_vector(6 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
NOMORE_DATA_OUT : out std_logic;
signal new_timestamp_delayed : std_logic_vector(31 downto 0);
signal new_adc_data_delayed : std_logic_vector(11 downto 0);
signal new_data_delayed : std_logic;
- signal new_data_delay_value : unsigned(6 downto 0);
+ signal new_data_fifo_delay : std_logic_vector(6 downto 0);
-- Data Validate
signal timestamp : std_logic_vector(13 downto 0);
others => x"0000"
),
- PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
+ PORT_ADDR_MASK => ( 0 => 4, -- Control Register Handler
1 => 0, -- I2C master
2 => 4, -- Data Receiver
3 => 3, -- Data Buffer
9 => 8, -- NX Register Setup
10 => 9, -- NX Histograms
11 => 0, -- Debug Handler
- 12 => 2, -- Data Delay
+ 12 => 1, -- Data Delay
others => 0
),
NX_FRAME_OUT => new_timestamp_delayed,
ADC_DATA_OUT => new_adc_data_delayed,
NEW_DATA_OUT => new_data_delayed,
- DATA_DELAY_VALUE_OUT => new_data_delay_value,
+ FIFO_DELAY_IN => new_data_fifo_delay,
SLV_READ_IN => slv_read(12),
SLV_WRITE_IN => slv_write(12),
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_validate_busy,
TIMESTAMP_REF_IN => timestamp_hold,
- DATA_DELAY_VALUE_IN => new_data_delay_value,
+ DATA_FIFO_DELAY_OUT => new_data_fifo_delay,
DATA_OUT => trigger_data,
DATA_CLK_OUT => trigger_data_clk,
nx_histograms_1: nx_histograms
generic map (
BUS_WIDTH => 7,
- ENABLE => 0
+ ENABLE => 1
)
port map (
CLK_IN => CLK_IN,
entity nxyter_registers is
port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- -- Signals
- I2C_SM_RESET_OUT : out std_logic;
- I2C_REG_RESET_OUT : out std_logic;
- NX_TS_RESET_OUT : out std_logic;
- OFFLINE_OUT : out std_logic;
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- Monitor PLL Locks
+ PLL_NX_CLK_LOCK_IN : in std_logic;
+ PLL_ADC_CLK_LOCK_1_IN : in std_logic;
+ PLL_ADC_CLK_LOCK_2_IN : in std_logic;
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ -- Signals
+ I2C_SM_RESET_OUT : out std_logic;
+ I2C_REG_RESET_OUT : out std_logic;
+ NX_TS_RESET_OUT : out std_logic;
+ OFFLINE_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end entity;
begin
- DEBUG_OUT(0) <= i2c_sm_reset_o ;
- DEBUG_OUT(1) <= i2c_reg_reset_o;
- DEBUG_OUT(2) <= nx_ts_reset_o;
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= i2c_sm_reset_o;
+ DEBUG_OUT(2) <= i2c_reg_reset_o;
+ DEBUG_OUT(3) <= nx_ts_reset_o;
- DEBUG_OUT(15 downto 3) <= (others => '0');
+ DEBUG_OUT(15 downto 4) <= (others => '0');
nx_timer_1: nx_timer
generic map (
nx_ts_reset_start <= '0';
offline_o <= '1';
else
- slv_ack_o <= '1';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
slv_data_out_o <= (others => '0');
case SLV_ADDR_IN is
when x"0000" =>
i2c_sm_reset_start <= '1';
+ slv_ack_o <= '1';
when x"0001" =>
i2c_reg_reset_start <= '1';
+ slv_ack_o <= '1';
when x"0002" =>
nx_ts_reset_start <= '1';
+ slv_ack_o <= '1';
when x"0003" =>
offline_o <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
when x"0003" =>
slv_data_out_o(0) <= offline_o;
slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0004" =>
+ slv_data_out_o(0) <= PLL_NX_CLK_LOCK_IN;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0005" =>
+ slv_data_out_o(0) <= PLL_ADC_CLK_LOCK_1_IN;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0006" =>
+ slv_data_out_o(0) <= PLL_ADC_CLK_LOCK_2_IN;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
end case;
else
- slv_ack_o <= '0';
+ slv_ack_o <= '0';
end if;
end if;
end if;
0x8101 : w w: reset I2C all Register
0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA)
0x8103 : r/w Put nxyter into offline mode
+0x8104 : r PLL Lock nXyter Main Clock (250MHz)
+0x8105 : r PLL Lock ADC Clock 1 (31.25MHz)
+0x8106 : r PLL Lock ADC Clock 2 (31.25MHz)
-- NX I2C Setup Handler
0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c)
0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO)
-- Trigger Generator
-0x8140 : w If writing just start trigger cycle, keep current setting
-0x8141 : r/w Bit 15-0 : periodic time (in 10ns)
-0x8142 : r/w Bit0 7-0 : number of triggers to be sent consecutive
+#0x8140 : w If writing just start trigger cycle, keep current setting
+#0x8141 : r/w Bit 15-0 : periodic time (in 10ns)
+#0x8142 : r/w Bit0 7-0 : number of triggers to be sent consecutive
0x8143 : r/w Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it
-0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger
+#0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger
0x8145 : r : Testpulse Rate (in Hz)
-- Trigger Handler
2: ADC Value Testchannel
3: ADC Reset Handler
0x8508 : r current ADC FIFO value
+0x8509 : r/w Enable Test ADC Input Data Error Test
+0x850a : r ADC Input Data Error Counter (16 Bit)
+ (only valid in case of 0x8509 is 1, see line above)
-- NX Data Delay
-0x8130 : r/w FIFO Delay, i.e. Trigger Delay (7Bit, in 31.25ns, Range 2..120)
- default: 10
+0x8130 : r FIFO Delay, i.e. Trigger Delay (7Bit, in 32ns, Range 1..120)
-- NX Data Validate
0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters
0x8121 : r Overflow Counter (16 bit)
0x8122 : r Pileup Counter (16 bit)
0x8123 : r Parity Error Counter (16 bit)
-0x8124 : r Trigger Rate (in Hz)
+0x8124 : r Hit Rate (in Hz)
0x8125 : r Frame Rate (in Hz)
-- NX Trigger Validate
-0x8180 : r/w Readout Mode (0:Ref + valid + window, 1: Ref + Valid
- 3: Raw and TimeStamp + valid,
- 4: Raw, 5: Raw + Valid )
-0x8181 : r/w Trigger Window Delay (12 bit, in 3.9ns)
-0x8182 : r/w Trigger Window Width (12 bit, in 3.9ns)
-0x8183 : r/w Readout Time Max (12 bit, in 10ns)
-0x8184 : r Busy Time Counter (12 bit, in 10ns)
+0x8180 : r/w Readout Mode (0: Ref + [DeltaTS + ovfl + parity] valid
+ 1: Ref + [DeltaTS + ovfl + pileup + parity] valid
+ 2: UNDEF
+ 3: UNDEF
+ 4: Ref + [ ovfl + + parity] valid
+ 5: Ref + [ ovfl + pileup + parity] valid
+ 6: UNDEF
+ 7: UNDEF
+0x8181 : r/w Trigger Window Delay (12 bit, in 4ns)
+0x8182 : r/w Trigger Window Width (12 bit, in 4ns)
+0x8183 : r/w CTS Trigger Delay (12 bit, in 4ns)
+0x8184 : r/w Readout Time Max (12 bit, in 10ns)
-0x8185 : r timestamp_ref
-0x8186 : r window_lower_thr
-0x8187 : r window_upper_thr
-0x8188 : r current Data Delay Value
-0x8189 : r done counter ch 0..31
-0x818a : r done counter ch 32..63
-0x818b : r done counter ch 94..95
-0x818c : r done counter ch 96..127
+0x8185 : r Busy Time Counter (12 bit, in 10ns)
+0x8186 : r timestamp_ref
+0x8187 : r window_lower_thr
+0x8188 : r window_upper_thr
+0x8189 : r data_fifo_delay (7 bit, in 32ns)
+0x818a : r done counter ch 0..31
+0x818b : r done counter ch 32..63
+0x818c : r done counter ch 94..95
+0x818d : r done counter ch 96..127
-- Event Data Buffer
0x8600 : r read FIFO buffer
architecture trb3_periph_arch of trb3_periph is
+
+ -- For 250MHz PLL nxyter clock, THE_250M_ODDR_1
+ -- attribute ODDRAPPS : string;
+ -- attribute ODDRAPPS of THE_250M_ODDR_1 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS of THE_250M_ODDR_2 : label is "SCLK_ALIGNED";
+
--Constants
constant REGIO_NUM_STAT_REGS : integer := 5;
constant REGIO_NUM_CTRL_REGS : integer := 3;
REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
- --BROADCAST_SPECIAL_ADDR => x"45",
- BROADCAST_SPECIAL_ADDR => x"48",
+ BROADCAST_SPECIAL_ADDR => x"49",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
REGIO_HARDWARE_VERSION => x"9100_6000",
- REGIO_INIT_ADDRESS => x"8900",
+ REGIO_INIT_ADDRESS => x"3800",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 125,
TIMING_TRIGGER_RAW => c_YES,
NX1_CLK256A_OUT <= nx_main_clk;
NX2_CLK256A_OUT <= nx_main_clk;
+ -- THE_250M_ODDR_1: ODDRXD1
+ -- port map(
+ -- SCLK => nx_main_clk,
+ -- DA => '1',
+ -- DB => '0',
+ -- Q => NX1_CLK256A_OUT
+ -- );
+ --
+ -- THE_250M_ODDR_2: ODDRXD1
+ -- port map(
+ -- SCLK => nx_main_clk,
+ -- DA => '1',
+ -- DB => '0',
+ -- Q => NX2_CLK256A_OUT
+ -- );
+
-- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
-- based on same ClockSource as nXyter Main Clock)
pll_adc_clk_1: pll_adc_clk
jspc29 / trb3.git / commitdiff