fpga_led_to_board : out std_logic_vector(3 downto 0);
fpga_aux_to_board : out std_logic_vector(9 downto 0);
+ --resets
+ timestampreset_in : in std_logic;
+ eventcounterreset_in : in std_logic;
+
--TRBv3 connections
TIMING_TRG_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
signal sout_d_from_mupix_sync : std_logic;
signal hbus_from_mupix_sync : std_logic;
signal fpga_aux_from_board_sync : std_logic_vector(9 downto 0);
-
+
begin -- Behavioral
sout_d_from_mupix_sync => sout_d_from_mupix_sync,
hbus_from_mupix_sync => hbus_from_mupix_sync,
fpga_aux_from_board_sync => fpga_aux_from_board_sync,
+
SLV_READ_IN => slv_read(7),
SLV_WRITE_IN => slv_write(7),
SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
memwren => memwren,
trigger_ext => valid_trigger_int,
ro_busy => ro_mupix_busy,
+ timestampreset_in => timestampreset_in,
+ eventcounterreset_in => eventcounterreset_in,
SLV_READ_IN => slv_read(0),
SLV_WRITE_IN => slv_write(0),
SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
--trigger
trigger_ext : in std_logic;
+ --reset signals from DAQ
+ timestampreset_in : in std_logic;
+ eventcounterreset_in : in std_logic;
+
--TRB SlowControl
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
readnow <= '0';
end if;
readmanual <= roregister(3);
- if(roregister(4) = '1' and roregwritten = '1') then
+ if((roregister(4) = '1' and roregwritten = '1') or eventcounterreset_in = '1') then
reseteventcount <= '1';
else
reseteventcount <= '0';
end if;
end process;
- resetgraycounter <= not rstn;
+ resetgraycounter <= not(rstn) or timestampreset_in;
grcount : Graycounter
generic map(
ro_busy <= ro_busy_int;
+
end RTL;
--- /dev/null
+------------------------------------------------------------
+--Module to Broadcast a Reset Signal to several frontends
+--entities on an peripherial FPGA.
+--T. Weber, University Mainz
+------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+--use work.trb3_components.all;
+--use work.version.all;
+
+entity resethandler is
+
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TimestampReset_OUT : out std_logic;
+ EventCounterReset_OUT : out std_logic;
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic);
+end entity resethandler;
+
+architecture behavioral of resethandler is
+
+ signal timestampreset_i : std_logic := '0';
+ signal eventcounterreset_i : std_logic := '0';
+ signal timestampreset_edge : std_logic_vector(1 downto 0) := (others => '0');
+ signal eventcounterreset_edge : std_logic_vector(1 downto 0) := (others => '0');
+
+begin -- architecture behavioral
+
+
+ timestamp_edge_detect : process (CLK_IN) is
+ begin -- process timestamp_edge_detect
+ if rising_edge(CLK_IN) then
+ timestampreset_edge <= timestampreset_edge(0) & timestampreset_i;
+ if timestampreset_edge = "01" then
+ TimestampReset_OUT <= '1';
+ else
+ TimestampReset_OUT <= '0';
+ end if;
+ end if;
+ end process timestamp_edge_detect;
+
+ eventcounter_edge_detect : process (CLK_IN) is
+ begin -- process eventcounter_edge_detect
+ if rising_edge(CLK_IN) then
+ eventcounterreset_edge <= eventcounterreset_edge(0) & eventcounterreset_i;
+ if eventcounterreset_edge = "01" then
+ EventCounterReset_OUT <= '1';
+ else
+ EventCounterReset_OUT <= '0';
+ end if;
+ end if;
+ end process eventcounter_edge_detect;
+
+ ------------------------------------------------------------
+ --TRB SLV-BUS Hanlder
+ ------------------------------------------------------------
+ --0x0001: reset timestamps
+ --0x0002: reset eventcounter
+ slv_bus_handler : process (CLK_IN) is
+ begin -- process slv_bus_handler
+ if rising_edge(CLK_IN) then
+ slv_data_out <= (others => '0');
+ slv_ack_out <= '0';
+ slv_no_more_data_out <= '0';
+ slv_unknown_addr_out <= '0';
+
+ if SLV_WRITE_IN = '1' then
+ case SLV_ADDR_IN is
+ when x"0001" =>
+ timestampreset_i <= SLV_DATA_IN(0);
+ slv_ack_out <= '1';
+ when x"0002" =>
+ eventcounterreset_i <= SLV_DATA_IN(0);
+ slv_ack_out <= '1';
+ when others =>
+ slv_unknown_addr_out <= '1';
+ end case;
+ end if;
+
+ if SLV_READ_IN = '1' then
+ case SLV_ADDR_IN is
+ when x"0001" =>
+ slv_data_out(0) <= timestampreset_i;
+ slv_ack_out <= '1';
+ when x"0002" =>
+ slv_data_out(0) <= eventcounterreset_i;
+ slv_ack_out <= '1';
+ when others =>
+ slv_unknown_addr_out <= '1';
+ end case;
+ end if;
+ end if;
+ end process slv_bus_handler;
+
+
+end architecture behavioral;
spi_ld_to_board : out std_logic;
fpga_led_to_board : out std_logic_vector(3 downto 0);
fpga_aux_to_board : out std_logic_vector(9 downto 0);
+ timestampreset_in : in std_logic;
+ eventcounterreset_in : in std_logic;
TIMING_TRG_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
LVL1_VALID_TIMING_TRG_IN : in std_logic;
memwren : out std_logic;
endofevent : out std_logic;
ro_busy : out std_logic;
- trigger_ext : in std_logic;
+ trigger_ext : in std_logic;
+ timestampreset_in : in std_logic;
+ eventcounterreset_in : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic);
end component;
-
+
--SPI entity to write Sensorboard DACs
component spi_if
port (
generic (
COUNTWIDTH : integer);
port (
- clk : in std_logic;
- reset : in std_logic;
- sync_reset : in std_logic;
- clk_divcounter : in std_logic_vector(7 downto 0);
- counter : out std_logic_vector(COUNTWIDTH-1 downto 0));
+ clk : in std_logic;
+ reset : in std_logic;
+ sync_reset : in std_logic;
+ clk_divcounter : in std_logic_vector(7 downto 0);
+ counter : out std_logic_vector(COUNTWIDTH-1 downto 0));
end component;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic);
end component board_interface;
+
+ component resethandler is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TimestampReset_OUT : out std_logic;
+ EventCounterReset_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic);
+ end component resethandler;
end mupix_components;
add_file -vhdl -lib "work" "sources/MuPix3_boardinterface.vhd"
add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd"
+add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
spi_ld_to_board0 : out std_logic;
fpga_led_to_board0 : out std_logic_vector(3 downto 0);
fpga_aux_to_board0 : out std_logic_vector(9 downto 0);
-
+
--Connections to Sensorboard 1
timestamp_from_mupix1 : in std_logic_vector(7 downto 0);
rowaddr_from_mupix1 : in std_logic_vector(5 downto 0);
TEST_LINE : out std_logic_vector(15 downto 0)
);
- attribute syn_useioff : boolean;
+ attribute syn_useioff : boolean;
--no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of TRIGGER_LEFT : signal is false;
- attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
--important signals
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_useioff of TEST_LINE : signal is true;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
--attribute syn_useioff of INP : signal is false;
--attribute syn_useioff of DAC_SDO : signal is true;
--attribute syn_useioff of DAC_SDI : signal is true;
--Constants
constant REGIO_NUM_STAT_REGS : integer := 5;
constant REGIO_NUM_CTRL_REGS : integer := 3;
- constant NumberFEECards : integer := 2;
+ constant NumberFEECards : integer := 2;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
signal mu_regio_no_more_data_out_1 : std_logic;
signal mu_regio_unknown_addr_out_1 : std_logic;
+ --common reset signals for mupix frontends
+ signal reset_timestamps_i : std_logic;
+ signal reset_eventcounters_i : std_logic;
+ signal resethandler_regio_addr_in_0 : std_logic_vector (15 downto 0);
+ signal resethandler_regio_data_in_0 : std_logic_vector (31 downto 0);
+ signal resethandler_regio_data_out_0 : std_logic_vector (31 downto 0);
+ signal resethandler_regio_read_enable_in_0 : std_logic;
+ signal resethandler_regio_write_enable_in_0 : std_logic;
+ signal resethandler_regio_timeout_in_0 : std_logic;
+ signal resethandler_regio_ack_out_0 : std_logic;
+ signal resethandler_regio_no_more_data_out_0 : std_logic;
+ signal resethandler_regio_unknown_addr_out_0 : std_logic;
begin
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000",
- 1 => x"d100",
- 2 => x"8000",
- 3 => x"9000",
- others => x"0000"),
- PORT_ADDR_MASK => (0 => 1,
- 1 => 6,
- 2 => 12,
- 3 => 12,
- others => 0)
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"d000",
+ 1 => x"d100",
+ 2 => x"8000", --Mupix 0
+ 3 => x"9000", --Mupix 1
+ 4 => x"c000", --Reset
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1,
+ 1 => 6,
+ 2 => 12,
+ 3 => 12,
+ 4 => 12,
+ others => 0)
)
port map(
CLK => clk_100_i,
BUS_NO_MORE_DATA_IN(3) => mu_regio_no_more_data_out_1,
BUS_UNKNOWN_ADDR_IN(3) => mu_regio_unknown_addr_out_1,
+ --Common Reset
+ BUS_READ_ENABLE_OUT(4) => resethandler_regio_read_enable_in_0,
+ BUS_WRITE_ENABLE_OUT(4) => resethandler_regio_write_enable_in_0,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => resethandler_regio_data_in_0,
+ BUS_ADDR_OUT(4*16+11 downto 4*16) => resethandler_regio_addr_in_0(11 downto 0),
+ BUS_ADDR_OUT(4*16+15 downto 4*16+12) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(4*32+31 downto 4*32) => resethandler_regio_data_out_0,
+ BUS_DATAREADY_IN(4) => resethandler_regio_ack_out_0,
+ BUS_WRITE_ACK_IN(4) => resethandler_regio_ack_out_0,
+ BUS_NO_MORE_DATA_IN(4) => resethandler_regio_no_more_data_out_0,
+ BUS_UNKNOWN_ADDR_IN(4) => resethandler_regio_unknown_addr_out_0,
+
STAT_DEBUG => open
);
fpga_led_to_board => fpga_led_to_board0,
fpga_aux_to_board => fpga_aux_to_board0,
+ timestampreset_in => reset_timestamps_i,
+ eventcounterreset_in => reset_eventcounters_i,
+
TIMING_TRG_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out_0,
REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_0);
- MuPix3_Board_1 : MuPix3_Board
+ MuPix3_Board_1 : MuPix3_Board
port map (
clk => clk_100_i,
reset => reset_i,
fpga_led_to_board => fpga_led_to_board1,
fpga_aux_to_board => fpga_aux_to_board1,
+ timestampreset_in => reset_timestamps_i,
+ eventcounterreset_in => reset_eventcounters_i,
+
TIMING_TRG_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out_1,
REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out_1);
-
+
+ resethandler_1 : entity work.resethandler
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ TimestampReset_OUT => reset_timestamps_i,
+ EventCounterReset_OUT => reset_eventcounters_i,
+ SLV_READ_IN => resethandler_regio_read_enable_in_0,
+ SLV_WRITE_IN => resethandler_regio_write_enable_in_0,
+ SLV_DATA_OUT => resethandler_regio_data_out_0,
+ SLV_DATA_IN => resethandler_regio_data_in_0,
+ SLV_ADDR_IN => resethandler_regio_addr_in_0,
+ SLV_ACK_OUT => resethandler_regio_ack_out_0,
+ SLV_NO_MORE_DATA_OUT => resethandler_regio_no_more_data_out_0,
+ SLV_UNKNOWN_ADDR_OUT => resethandler_regio_unknown_addr_out_0);
end architecture;
jspc29 / trb3.git / commitdiff