fifo_term_buffer_data_out <= (others => '0');
end generate CHECK_BUFFER2;
-
+
+ --BUGBUG here we should use the trb_net_term entity
FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN,
INT_INIT_DATAREADY_IN, tb_next_registered_trailer,
--- /dev/null
+-- this is the final endpoint to be used
+-- It has 3 channels
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net_endpoint_3ch is
+
+ -- per channel we have the following generics:
+ -- 1.) APIX_FIFO_TO_INT_DEPTH
+ -- 2.) APIX_FIFO_TO_APL_DEPTH
+ -- 3.) APIX_TYPE (0=active, 1=passive, 99=dummy)
+ -- 4.) APIX_INIT_DEPTH
+ -- 5.) APIX_REPLY_DEPTH
+ -- 6.) APIX_CHANNEL_NUMBER
+
+ -- The dummy APL can be used for debugging
+ -- In this case, the API lines are use only for sniffing
+ -- and the input lines can be driven to any value
+ -- with one exeption:
+ -- if APL_SEND_IN = '0' the dummy APL will be resetted
+
+ generic (
+
+ API1_FIFO_TO_INT_DEPTH: integer := 3;
+ API1_FIFO_TO_APL_DEPTH: integer := 3;
+ API1_TYPE : integer := 0;
+ API1_INIT_DEPTH : integer := 3;
+ API1_REPLY_DEPTH : integer := 3;
+ API1_CHANNEL_NUMBER : integer := 0;
+
+ API2_FIFO_TO_INT_DEPTH: integer := 3;
+ API2_FIFO_TO_APL_DEPTH: integer := 3;
+ API2_TYPE : integer := 0;
+ API2_INIT_DEPTH : integer := 3;
+ API2_REPLY_DEPTH : integer := 3;
+ API2_CHANNEL_NUMBER : integer := 1;
+
+ API3_FIFO_TO_INT_DEPTH: integer := 3;
+ API3_FIFO_TO_APL_DEPTH: integer := 3;
+ API3_TYPE : integer := 0;
+ API3_INIT_DEPTH : integer := 3;
+ API3_REPLY_DEPTH : integer := 3;
+ API3_CHANNEL_NUMBER : integer := 2;
+
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ ----------------------------------------------------------------------------
+ -- API1
+ ----------------------------------------------------------------------------
+ -- APL Transmitter port
+ APL1_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL1_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
+ APL1_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
+ APL1_SHORT_TRANSFER_IN: in STD_LOGIC; --
+ APL1_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL1_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL1_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL1_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL1_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL1_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL1_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
+ APL1_READ_IN: in STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL1_RUN_OUT: out STD_LOGIC; -- Data transfer is running
+ APL1_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+
+ ----------------------------------------------------------------------------
+ -- API2
+ ----------------------------------------------------------------------------
+ -- APL Transmitter port
+ APL2_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL2_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
+ APL2_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
+ APL2_SHORT_TRANSFER_IN: in STD_LOGIC; --
+ APL2_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL2_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL2_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL2_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL2_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL2_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL2_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
+ APL2_READ_IN: in STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL2_RUN_OUT: out STD_LOGIC; -- Data transfer is running
+ APL2_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+
+ ----------------------------------------------------------------------------
+ -- API3
+ ----------------------------------------------------------------------------
+ -- APL Transmitter port
+ APL3_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL3_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
+ APL3_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
+ APL3_SHORT_TRANSFER_IN: in STD_LOGIC; --
+ APL3_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL3_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL3_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL3_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL3_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL3_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL3_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
+ APL3_READ_IN: in STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL3_RUN_OUT: out STD_LOGIC; -- Data transfer is running
+ APL3_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+
+
+ ----------------------------------------------------------------------------
+ -- Common API stuff
+ ----------------------------------------------------------------------------
+ APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
+ APL_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+
+ -- IOBUF ports missing -> Later (BUGBUG)
+
+ APL_GOT_TRM : out STD_LOGIC_VECTOR (15 downto 0); --pattern from the
+ --unused TERMs
+ APL_HOLD_TRM: in STD_LOGIC_VECTOR (15 downto 0); --put to "0"
+
+ ---------------------------------------------------------------------------
+ -- Media direction port (directly to be connected to MII)
+ ---------------------------------------------------------------------------
+ MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word
+ MED_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END trb_net_endpoint_3ch;
+
+architecture trb_net_endpoint_3ch_arch of trb_net_endpoint_3ch is
+
+ component trb_net_io_multiplexer is
+
+ generic (BUS_WIDTH : integer := 56;
+ MULT_WIDTH : integer := 5);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in STD_LOGIC;
+ MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_READ_OUT: out STD_LOGIC;
+
+ MED_DATAREADY_OUT: out STD_LOGIC;
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ MED_READ_IN: in STD_LOGIC;
+
+ -- Internal direction port
+ INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT: out STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+component trb_net_active_apimbuf is
+
+ generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 3; -- or the replyibuf
+ FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+
+ -- APL Transmitter port
+ APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
+ APL_READ_IN: in STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+component trb_net_term_mbuf is
+
+ generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+ APL_GOT_TRM: out STD_LOGIC;
+
+ APL_HOLD_TRM: in STD_LOGIC;
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+-- for the connection to the multiplexer
+signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
+signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_IN : STD_LOGIC;
+
+signal MED_INIT_DATAREADY_IN : STD_LOGIC;
+signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_OUT : STD_LOGIC;
+
+signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
+signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_IN : STD_LOGIC;
+
+signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
+signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_OUT : STD_LOGIC;
+
+signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (15 downto 0);
+signal m_DATA_OUT : STD_LOGIC_VECTOR (831 downto 0);
+signal m_READ_IN : STD_LOGIC_VECTOR (15 downto 0);
+
+signal m_DATAREADY_IN : STD_LOGIC_VECTOR (15 downto 0);
+signal m_DATA_IN : STD_LOGIC_VECTOR (831 downto 0);
+signal m_READ_OUT : STD_LOGIC_VECTOR (15 downto 0);
+
+begin
+
+
+-- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
+-- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
+-- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
+-- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
+-- MED_INIT_READ_IN <= m_READ_IN(0);
+-- MED_REPLY_READ_IN <= m_READ_IN(1);
+
+-- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
+-- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
+-- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
+-- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
+-- m_READ_OUT(0) <= MED_INIT_READ_OUT;
+-- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
+
+ G1: for channel in 0 to 15 generate
+-------------------------------------------------------------------------------
+-- loop over the channels
+-------------------------------------------------------------------------------
+ GEN_API1: if not channel = API1_CHANNEL_NUMBER
+ and not channel = API2_CHANNEL_NUMBER
+ and not channel = API3_CHANNEL_NUMBER
+ generate
+ -- make the term
+ TERM: trb_net_term_mbuf
+
+ generic map (FIFO_TERM_BUFFER_DEPTH => 0 )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET ,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_DATAREADY_OUT => m_DATAREADY_OUT(channel),
+ MED_DATA_OUT => m_DATA_OUT(channel*52+51 downto channel*52),
+ MED_READ_IN => m_READ_IN(channel),
+
+ MED_DATAREADY_IN => m_DATAREADY_IN(channel),
+ MED_DATA_IN => m_DATA_IN(channel*52+51 downto channel*52),
+ MED_READ_OUT => m_READ_OUT(channel),
+ MED_ERROR_IN => (others => '0'),
+
+ APL_GOT_TRM => APL_GOT_TRM(channel),
+
+ APL_HOLD_TRM => APL_HOLD_TRM(channel),
+ APL_DTYPE_IN => (others => '0'),
+ APL_ERROR_PATTERN_IN => (others => '0'),
+
+ CTRL_GEN => (others => '0'),
+ CTRL_LOCKED => (others => '0'),
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER=> (others => '0'),
+ MPLEX_CTRL => APL_MPLEX_CTRL );
+ end generate;
+ end generate;
+
+ MPLEX: trb_net_io_multiplexer
+ generic map (BUS_WIDTH => 56,
+ MULT_WIDTH => 4)
+ port map (
+ CLK => CLK,
+ RESET => RESET ,
+ CLK_EN => CLK_EN,
+
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_READ_OUT => MED_READ_OUT,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_READ_IN => MED_READ_IN,
+
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_READ_IN =>m_READ_OUT,
+
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_READ_OUT =>m_READ_IN,
+
+ CTRL => MED_MPLEX_CTRL
+ );
+
+API1: trb_net_active_apimbuf
+
+ generic map (INIT_DEPTH => API1_INIT_DEPTH,
+ REPLY_DEPTH => API1_REPLY_DEPTH,
+ FIFO_TO_INT_DEPTH => API1_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => API1_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0
+ )
+
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_DATAREADY_OUT => m_DATAREADY_OUT(API1_CHANNEL_NUMBER),
+ MED_DATA_OUT => m_DATA_OUT(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52),
+ MED_READ_IN => m_READ_IN(API1_CHANNEL_NUMBER),
+
+ MED_DATAREADY_IN => m_DATAREADY_IN(API1_CHANNEL_NUMBER),
+ MED_DATA_IN => m_DATA_IN(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52),
+ MED_READ_OUT => m_READ_OUT(API1_CHANNEL_NUMBER),
+ MED_ERROR_IN => (others => '0'),
+
+ -- APL Transmitter port
+ APL_DATA_IN => APL1_DATA_IN,
+ APL_WRITE_IN => APL1_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL1_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL1_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL1_TARGET_ADDRESS_IN,
+
+ -- Receiver port
+ APL_DATA_OUT => APL1_DATA_OUT,
+ APL_TYP_OUT => APL1_TYP_OUT,
+ APL_DATAREADY_OUT => APL1_DATAREADY_OUT,
+ APL_READ_IN => APL1_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL1_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL1_SEQNR_OUT,
+
+ CTRL_GEN => (others => '0'),
+ CTRL_LOCKED => (others => '0'),
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER=> (others => '0'),
+ MPLEX_CTRL => APL_MPLEX_CTRL
+ );
+
+API2: trb_net_active_apimbuf
+
+ generic map (INIT_DEPTH => API2_INIT_DEPTH,
+ REPLY_DEPTH => API2_REPLY_DEPTH,
+ FIFO_TO_INT_DEPTH => API2_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => API2_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0
+ )
+
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_DATAREADY_OUT => m_DATAREADY_OUT(API2_CHANNEL_NUMBER),
+ MED_DATA_OUT => m_DATA_OUT(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52),
+ MED_READ_IN => m_READ_IN(API2_CHANNEL_NUMBER),
+
+ MED_DATAREADY_IN => m_DATAREADY_IN(API2_CHANNEL_NUMBER),
+ MED_DATA_IN => m_DATA_IN(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52),
+ MED_READ_OUT => m_READ_OUT(API2_CHANNEL_NUMBER),
+ MED_ERROR_IN => (others => '0'),
+
+ -- APL Transmitter port
+ APL_DATA_IN => APL2_DATA_IN,
+ APL_WRITE_IN => APL2_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL2_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL2_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL2_TARGET_ADDRESS_IN,
+
+ -- Receiver port
+ APL_DATA_OUT => APL2_DATA_OUT,
+ APL_TYP_OUT => APL2_TYP_OUT,
+ APL_DATAREADY_OUT => APL2_DATAREADY_OUT,
+ APL_READ_IN => APL2_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL2_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL2_SEQNR_OUT,
+
+ CTRL_GEN => (others => '0'),
+ CTRL_LOCKED => (others => '0'),
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER=> (others => '0'),
+ MPLEX_CTRL => APL_MPLEX_CTRL
+ );
+
+API3: trb_net_active_apimbuf
+
+ generic map (INIT_DEPTH => API3_INIT_DEPTH,
+ REPLY_DEPTH => API3_REPLY_DEPTH,
+ FIFO_TO_INT_DEPTH => API3_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => API3_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0
+ )
+
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_DATAREADY_OUT => m_DATAREADY_OUT(API3_CHANNEL_NUMBER),
+ MED_DATA_OUT => m_DATA_OUT(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52),
+ MED_READ_IN => m_READ_IN(API3_CHANNEL_NUMBER),
+
+ MED_DATAREADY_IN => m_DATAREADY_IN(API3_CHANNEL_NUMBER),
+ MED_DATA_IN => m_DATA_IN(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52),
+ MED_READ_OUT => m_READ_OUT(API3_CHANNEL_NUMBER),
+ MED_ERROR_IN => (others => '0'),
+
+ -- APL Transmitter port
+ APL_DATA_IN => APL3_DATA_IN,
+ APL_WRITE_IN => APL3_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL3_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL3_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL3_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL3_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL3_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL3_TARGET_ADDRESS_IN,
+
+ -- Receiver port
+ APL_DATA_OUT => APL3_DATA_OUT,
+ APL_TYP_OUT => APL3_TYP_OUT,
+ APL_DATAREADY_OUT => APL3_DATAREADY_OUT,
+ APL_READ_IN => APL3_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL3_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL3_SEQNR_OUT,
+
+ CTRL_GEN => (others => '0'),
+ CTRL_LOCKED => (others => '0'),
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER=> (others => '0'),
+ MPLEX_CTRL => APL_MPLEX_CTRL
+ );
+
+
+end trb_net_endpoint_3ch_arch;
+
signal fifo_full, fifo_empty : std_logic;
signal fifo_depth : std_logic_vector(7 downto 0);
-signal filtered_dataready : std_logic;
signal next_read_out, reg_read_out : std_logic;
signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack
fifo_full, is_locked, current_rec_buffer_size_out,
current_error_state)
begin -- process
- filtered_dataready <= '0';
got_ack_internal <= '0';
next_read_out <= '0';
fifo_write <= '0';
next_error_state <= GOT_OVERFLOW_ERROR;
elsif is_locked = '1' then
next_error_state <= GOT_LOCKED_ERROR;
- else
- next_error_state <= GOT_UNDEFINED_ERROR;
end if; -- end TYPE
end if; -- end MED_DATAREADY_IN
if fifo_full = '0' then -- and is_locked = '0' then
);
END component;
+ component trb_net_term_ibuf is
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
+ INT_DATAREADY_OUT: out STD_LOGIC;
+ INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_IN: in STD_LOGIC;
+ INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+ -- Status and control port
+ STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
+ );
+ END component;
+
component trb_net_obuf is
port(
begin
+ GEN_IBUF: if INIT_DEPTH>0 generate
+
INITIBUF : trb_net_ibuf
generic map (
- DEPTH => 3)
+ DEPTH => INIT_DEPTH)
port map (
CLK => CLK,
RESET => RESET,
REPLYIBUF : trb_net_ibuf
generic map (
- DEPTH => 3)
+ DEPTH => REPLY_DEPTH)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_DATA_IN => MED_REPLY_DATA_IN,
+ MED_READ_OUT => MED_REPLY_READ_OUT,
+ MED_ERROR_IN => MED_REPLY_ERROR_IN,
+ INT_HEADER_IN => INT_REPLY_HEADER_IN,
+ INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
+ INT_DATA_OUT => INT_REPLY_DATA_OUT,
+ INT_READ_IN => INT_REPLY_READ_IN,
+ INT_ERROR_OUT => REPLYIBUF_error,
+ STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked,
+ CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked,
+ STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer
+ );
+
+ end generate;
+
+ GEN_TERM_IBUF: if DEPTH=0 generate
+
+ INITIBUF : trb_net_term_ibuf
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_DATA_IN => MED_INIT_DATA_IN,
+ MED_READ_OUT => MED_INIT_READ_OUT,
+ MED_ERROR_IN => MED_INIT_ERROR_IN,
+ INT_HEADER_IN => '0',
+ INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
+ INT_DATA_OUT => INT_INIT_DATA_OUT,
+ INT_READ_IN => INT_INIT_READ_IN,
+ INT_ERROR_OUT => INITIBUF_error,
+ STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked,
+ CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
+ STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
+ );
+
+ REPLYIBUF : trb_net_term_ibuf
port map (
CLK => CLK,
RESET => RESET,
STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer
);
+ end generate;
+
INITOBUF : trb_net_obuf
port map (
CLK => CLK,
next_max_DATA_COUNT_minus_one <= (0 => '1', others => '0');
else
max_DATA_COUNT <= next_max_DATA_COUNT;
- next_max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one;
+ max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one;
end if;
end if;
end process;
subtype F3_POSITION is integer range 15 downto 0;
subtype DWORD_POSITION is integer range 47 downto 0;
+-- this is for TRM
+ subtype DTYPE_POSITION is integer range 3 downto 0;
+ subtype SEQNR_POSITION is integer range 11 downto 4;
+ subtype ERRORPATTERN_POSITION is integer range 47 downto 16;
+
subtype SOURCE_POSITION is integer range 47 downto 32;
subtype TARGET_POSITION is integer range 31 downto 16;
--- /dev/null
+-- this is just a terminator, which auto-answers requests
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net_term is
+
+ generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Internal direction port
+ -- This is just a clone from trb_net_iobuf
+
+ INT_DATAREADY_OUT: out STD_LOGIC;
+ INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_IN: in STD_LOGIC;
+
+ INT_DATAREADY_IN: in STD_LOGIC;
+ INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_OUT: out STD_LOGIC;
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+ APL_GOT_TRM: out STD_LOGIC;
+
+ APL_HOLD_TRM: in STD_LOGIC;
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
+
+
+ -- Status and control port
+
+ -- not needed now, but later
+
+ );
+END trb_net_term;
+
+architecture trb_net_term_arch of trb_net_term is
+
+component trb_net_fifo is
+ generic (WIDTH : integer := 8; -- FIFO word width
+ DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
+
+ port (CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic; -- Full Flag
+ EMPTY_OUT : out std_logic;
+ DEPTH_OUT : out std_logic_vector(7 downto 0)
+ );
+
+ end component;
+
+-- signals for the test buffer
+signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic;
+signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic;
+signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic;
+signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic;
+
+signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0);
+signal fifo_term_buffer_write : std_logic;
+signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0);
+signal fifo_term_buffer_read : std_logic;
+signal fifo_term_buffer_full : std_logic;
+signal fifo_term_buffer_empty : std_logic;
+
+type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR);
+signal tb_current_state, tb_next_state : TERM_BUFFER_STATE;
+
+-- signal combined_header, registered_header, next_registered_header: std_logic_vector(47 downto 0);
+-- signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0);
+ signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0);
+ signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0);
+
+-- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
+-- signal next_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0);
+-- signal next_INT_INIT_DATAREADY_OUT: std_logic;
+-- signal sbuf_free, sbuf_next_READ: std_logic;
+ signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic;
+-- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
+-- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0);
+-- signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0);
+
+begin
+
+
+CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate
+ FIFO_TERM_BUFFER: trb_net_fifo
+ generic map (
+ WIDTH => 51,
+ DEPTH => FIFO_TERM_BUFFER_DEPTH)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ DATA_IN => fifo_term_buffer_data_in,
+ WRITE_ENABLE_IN => fifo_term_buffer_write,
+ DATA_OUT => fifo_term_buffer_data_out,
+ READ_ENABLE_IN => fifo_term_buffer_read,
+ FULL_OUT => fifo_term_buffer_full,
+ EMPTY_OUT => fifo_term_buffer_empty
+ );
+end generate CHECK_BUFFER1;
+CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate
+ fifo_term_buffer_empty <= '1';
+ fifo_term_buffer_full <= '0';
+ fifo_term_buffer_data_out <= (others => '0');
+
+end generate CHECK_BUFFER2;
+
+ APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
+ APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
+ APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
+ APL_GOT_TRM <= reg_APL_GOT_TRM;
+
+
+ FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN,
+ INT_INIT_DATAREADY_IN, tb_next_registered_trailer,
+ tb_registered_trailer,
+ fifo_term_buffer_empty, fifo_term_buffer_data_out,
+ INT_REPLY_READ_IN, tb_registered_target,
+ reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT,
+ reg_APL_SEQNR_OUT, reg_APL_GOT_TRM)
+ begin -- process
+ INT_INIT_READ_OUT <= '0';
+ fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL;
+ fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0');
+ fifo_term_buffer_write <= '0';
+ tb_next_state <= MY_ERROR;
+ tb_next_registered_trailer <= tb_registered_trailer;
+ tb_next_registered_target <= tb_registered_target;
+ fifo_term_buffer_read<= '0';
+ INT_REPLY_DATAREADY_OUT <= '0';
+ INT_REPLY_DATA_OUT(DWORD_POSITION) <= (others => '0');
+ INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
+ next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT;
+ next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
+ next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT;
+ next_APL_GOT_TRM <= reg_APL_GOT_TRM;
+-----------------------------------------------------------------------
+-- IDLE
+-----------------------------------------------------------------------
+ if tb_current_state = IDLE then
+ INT_INIT_READ_OUT <= '1'; -- I always can read
+ tb_next_state <= IDLE;
+ if INT_INIT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_INIT_DATAREADY_IN = '1' then
+ -- switch source and target adress
+ fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_INIT_DATA_IN(TARGET_POSITION);
+ fifo_term_buffer_data_in(TARGET_POSITION) <= INT_INIT_DATA_IN(SOURCE_POSITION);
+ fifo_term_buffer_data_in(F3_POSITION) <= INT_INIT_DATA_IN(F3_POSITION);
+ fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR;
+ tb_next_registered_target <= INT_INIT_DATA_IN(TARGET_POSITION);
+ if fifo_term_buffer_full = '0' and (INT_INIT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN
+ or INT_INIT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then
+ fifo_term_buffer_write <= '1';
+ else
+ fifo_term_buffer_write <= '0';
+ end if;
+ elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_INIT_DATAREADY_IN = '1' then
+ fifo_term_buffer_data_in <= INT_INIT_DATA_IN;
+ if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN
+ or tb_registered_target = BROADCAST_ADRESS) then
+ fifo_term_buffer_write <= '1';
+ else
+ fifo_term_buffer_write <= '0';
+ end if;
+ elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_INIT_DATAREADY_IN = '1' then
+ --tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION);
+ --keep trailer for later use
+ -- in addition, write out some debug info
+ next_APL_DTYPE_OUT <= INT_INIT_DATA_IN(DTYPE_POSITION);
+ next_APL_ERROR_PATTERN_OUT <= INT_INIT_DATA_IN(ERRORPATTERN_POSITION);
+ next_APL_SEQNR_OUT <= INT_INIT_DATA_IN(SEQNR_POSITION);
+ next_APL_GOT_TRM <= '1';
+ tb_next_state <= RUNNING;
+ end if;
+-----------------------------------------------------------------------
+-- RUNNING
+-----------------------------------------------------------------------
+ elsif tb_current_state = RUNNING then
+ tb_next_state <= RUNNING;
+ if fifo_term_buffer_empty = '0' then -- Have buffered stuff
+ INT_REPLY_DATAREADY_OUT <= '1';
+ INT_REPLY_DATA_OUT <= fifo_term_buffer_data_out;
+ if (INT_REPLY_READ_IN = '1') then
+ fifo_term_buffer_read <= '1';
+ end if;
+ elsif APL_HOLD_TRM = '1' then
+ tb_next_state <= RUNNING; --hold the line
+ else
+ tb_next_state <= SEND_TRAILER;
+ tb_next_registered_trailer(DTYPE_POSITION) <= APL_DTYPE_IN;
+ tb_next_registered_trailer(ERRORPATTERN_POSITION) <= APL_ERROR_PATTERN_IN;
+ tb_next_registered_trailer(SEQNR_POSITION) <= reg_APL_SEQNR_OUT;
+ tb_next_registered_trailer(15 downto 12) <= (others => '0');
+ end if; -- Have buffered stuff
+-----------------------------------------------------------------------
+-- TRAILER
+-----------------------------------------------------------------------
+ elsif tb_current_state = SEND_TRAILER then
+ tb_next_state <= SEND_TRAILER ;
+ INT_REPLY_DATAREADY_OUT <= '1';
+ INT_REPLY_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer;
+ INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
+ if (INT_REPLY_READ_IN = '1') then
+ tb_next_state <= IDLE;
+ tb_next_registered_target <= ILLEGAL_ADRESS;
+ next_APL_GOT_TRM <= '0';
+ end if;
+ end if; -- tb_current_state switch
+ end process;
+
+CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ tb_current_state <= IDLE;
+ tb_registered_trailer <= (others => '0');
+ tb_registered_target <= ILLEGAL_ADRESS;
+ reg_APL_DTYPE_OUT <= (others => '0');
+ reg_APL_ERROR_PATTERN_OUT <= (others => '0');
+ reg_APL_SEQNR_OUT <= (others => '0');
+ reg_APL_GOT_TRM <= '0';
+ else
+ tb_current_state <= tb_next_state;
+ tb_registered_trailer <= tb_next_registered_trailer;
+ tb_registered_target <= tb_next_registered_target;
+ reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT;
+ reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT;
+ reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT;
+ reg_APL_GOT_TRM <= next_APL_GOT_TRM;
+ end if;
+ end if;
+ end process;
+
+end trb_net_term_arch;
--- /dev/null
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
+-- This has in principle the same output ports, but internally
+-- it keeps only the TRM words
+-- EOB are killed
+-- ACK are regognized
+-- all other words (HDR, DAT) are not stored
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net_term_ibuf is
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header
+ INT_DATAREADY_OUT: out STD_LOGIC;
+ INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_IN: in STD_LOGIC;
+ INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+ -- Status and control port
+ STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
+ );
+END trb_net_term_ibuf;
+
+architecture trb_net_term_ibuf_arch of trb_term_net_ibuf is
+
+ component trb_net_sbuf is
+
+ generic (DATA_WIDTH : integer := 56);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+ END component;
+
+
+signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack
+ --arrived
+signal is_locked, got_locked,release_locked : std_logic;
+signal got_eob_out, reg_eob_out: std_logic;
+signal sbuf_free, comb_next_read: std_logic;
+signal tmp_INT_DATAREADY_OUT: std_logic;
+signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0);
+
+type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR);
+signal current_error_state, next_error_state : ERROR_STATE;
+
+signal next_rec_buffer_size_out, current_rec_buffer_size_out
+ : std_logic_vector(3 downto 0); -- buffer size control
+
+ begin
+
+
+-- this process controls the writing of the media into the fifo
+ FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN,
+ is_locked, current_rec_buffer_size_out,
+ current_error_state, release_locked,
+ sbuf_free)
+ begin -- process
+ got_ack_internal <= '0';
+ next_rec_buffer_size_out <= current_rec_buffer_size_out;
+ next_error_state <= current_error_state;
+ tmp_INT_DATA_OUT <= (others => '1');
+ tmp_INT_DATAREADY_OUT <= '0';
+ got_eob_out <= '0';
+ got_locked <= is_locked;
+
+ if MED_DATAREADY_IN = '1' then -- data word offered
+ if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
+ got_ack_internal <= '1';
+ if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
+ next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
+ end if;
+ elsif MED_DATA_IN(TYPE_POSITION) = TYPE_TRM then
+ got_eob_out <= '1'; --exactly when buffer is killed
+ tmp_INT_DATA_OUT <= MED_DATA_IN;
+ tmp_INT_DATAREADY_OUT <= '1';
+ if release_locked = '0' then
+ got_locked <= '1';
+ end if;
+ elsif MED_DATA_IN(TYPE_POSITION) = TYPE_EOB then
+ got_eob_out <= '1';
+ tmp_INT_DATAREADY_OUT <= '0';
+ -- this should happen only one CLK cycle
+ elsif sbuf_free = '0' then
+ next_error_state <= GOT_OVERFLOW_ERROR;
+ elsif is_locked = '1' then
+ next_error_state <= GOT_LOCKED_ERROR;
+ end if; -- end TYPE
+ end if; -- end MED_DATAREADY_IN
+ end process;
+
+ MED_READ_OUT <= '1'; -- I always can read
+
+reg_buffer: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_rec_buffer_size_out <= (others => '0');
+ reg_ack_internal <= '0';
+ current_error_state <= IDLE;
+ elsif CLK_EN = '1' then
+ current_rec_buffer_size_out <= next_rec_buffer_size_out;
+ reg_ack_internal <= got_ack_internal;
+ current_error_state <= next_error_state;
+ else
+ current_rec_buffer_size_out <= current_rec_buffer_size_out;
+ reg_ack_internal <= reg_ack_internal;
+ current_error_state <= current_error_state;
+ end if;
+ end if;
+ end process;
+
+
+
+ SBUF: trb_net_sbuf
+ generic map (DATA_WIDTH => 51)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT,
+ COMB_next_READ_OUT => comb_next_read,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => tmp_INT_DATA_OUT,
+ SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
+ SYN_DATA_OUT => INT_DATA_OUT,
+ SYN_READ_IN => INT_READ_IN,
+ CTRL_BUFFER => (others => '0')
+ );
+
+ sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
+
+release_locked <= CTRL_LOCKED(0);
+STAT_LOCKED(0) <= is_locked;
+STAT_LOCKED(15 downto 1) <= (others => '0');
+
+reg_locked: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ is_locked <= '0';
+ reg_eob_out <= '0';
+ current_last_header <= (others => '0');
+ elsif CLK_EN = '1' then
+ if release_locked = '1' then
+ is_locked <= '0';
+ else
+ is_locked <= got_locked;
+ end if;
+ reg_eob_out <= got_eob_out;
+ current_last_header <= next_last_header;
+ else
+ is_locked <= is_locked;
+ reg_eob_out <= reg_eob_out;
+ current_last_header <= current_last_header;
+ end if;
+ end if;
+ end process;
+
+
+
+-- make STAT_BUFFER
+-- STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2
+ --buffers have to be stored
+ STAT_BUFFER(3 downto 0) <= "0111"; --always "biggest fifo"
+ STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out;
+
+ STAT_BUFFER(8) <= reg_eob_out;
+ STAT_BUFFER(9) <= reg_ack_internal;
+
+ MAKE_ERROR_BITS : process(current_error_state)
+ begin
+ if current_error_state = IDLE then
+ STAT_BUFFER(11 downto 10) <= "00";
+ elsif current_error_state = GOT_OVERFLOW_ERROR then
+ STAT_BUFFER(11 downto 10) <= "01";
+ elsif current_error_state = GOT_LOCKED_ERROR then
+ STAT_BUFFER(11 downto 10) <= "10";
+ else
+ STAT_BUFFER(11 downto 10) <= "11";
+ end if;
+ end process;
+
+ STAT_BUFFER(31 downto 12) <= (others => '0');
+
+end trb_net_term_ibuf_arch;
+
--- /dev/null
+-- an active api together with an iobuf
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net_term_mbuf is
+
+ generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
+ MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+ APL_GOT_TRM: out STD_LOGIC;
+
+ APL_HOLD_TRM: in STD_LOGIC;
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END trb_net_term_mbuf;
+
+architecture trb_net_term_mbuf_arch of trb_net_term_mbuf is
+
+component trb_net_iobuf is
+
+ generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 3); -- or the replyibuf
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out STD_LOGIC;
+ INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_INIT_READ_IN: in STD_LOGIC;
+
+ INT_INIT_DATAREADY_IN: in STD_LOGIC;
+ INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_INIT_READ_OUT: out STD_LOGIC;
+
+ INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
+ INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_REPLY_READ_IN: in STD_LOGIC;
+
+ INT_REPLY_DATAREADY_IN: in STD_LOGIC;
+ INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_REPLY_READ_OUT: out STD_LOGIC;
+
+ -- Status and control port
+ STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+component trb_net_term is
+
+ generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Internal direction port
+ -- This is just a clone from trb_net_iobuf
+
+ INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_DATAREADY_OUT: out STD_LOGIC;
+ INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_IN: in STD_LOGIC;
+
+ INT_DATAREADY_IN: in STD_LOGIC;
+ INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ INT_READ_OUT: out STD_LOGIC;
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+ APL_GOT_TRM: out STD_LOGIC;
+
+ APL_HOLD_TRM: in STD_LOGIC;
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr
+
+
+ -- Status and control port
+
+ -- not needed now, but later
+
+ );
+END component;
+
+component trb_net_io_multiplexer is
+
+ generic (BUS_WIDTH : integer := 56;
+ MULT_WIDTH : integer := 5);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in STD_LOGIC;
+ MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_READ_OUT: out STD_LOGIC;
+
+ MED_DATAREADY_OUT: out STD_LOGIC;
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ MED_READ_IN: in STD_LOGIC;
+
+ -- Internal direction port
+ INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT: out STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+signal apl_to_buf_INIT_DATAREADY: STD_LOGIC;
+signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
+signal apl_to_buf_INIT_READ : STD_LOGIC;
+
+signal buf_to_apl_INIT_DATAREADY: STD_LOGIC;
+signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0);
+signal buf_to_apl_INIT_READ : STD_LOGIC;
+
+signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC;
+signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
+signal apl_to_buf_REPLY_READ : STD_LOGIC;
+
+signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC;
+signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0);
+signal buf_to_apl_REPLY_READ : STD_LOGIC;
+
+-- for the connection to the multiplexer
+signal MED_INIT_DATAREADY_OUT : STD_LOGIC;
+signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_IN : STD_LOGIC;
+
+signal MED_INIT_DATAREADY_IN : STD_LOGIC;
+signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_OUT : STD_LOGIC;
+
+signal MED_REPLY_DATAREADY_OUT : STD_LOGIC;
+signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_IN : STD_LOGIC;
+
+signal MED_REPLY_DATAREADY_IN : STD_LOGIC;
+signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_OUT : STD_LOGIC;
+
+signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0);
+signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0);
+signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0);
+
+signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0);
+signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0);
+signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0);
+
+begin
+
+ m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
+ m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT;
+ MED_INIT_READ_IN <= m_READ_IN(0);
+ MED_REPLY_READ_IN <= m_READ_IN(1);
+
+ MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
+ MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
+ MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0);
+ MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51);
+ m_READ_OUT(0) <= MED_INIT_READ_OUT;
+ m_READ_OUT(1) <= MED_REPLY_READ_OUT;
+
+
+ TERM_INIT: trb_net_term
+
+ generic map (FIFO_TERM_BUFFER_DEPTH => 0)
+
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => APL_DTYPE_OUT,
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ APL_GOT_TRM => APL_GOT_TRM,
+
+ APL_HOLD_TRM => APL_HOLD_TRM,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+
+ -- Internal direction port
+ -- connect via private signals
+
+ INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_INIT_DATA,
+ INT_READ_IN => apl_to_buf_INIT_READ,
+
+ INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
+ INT_DATA_IN => buf_to_apl_INIT_DATA,
+ INT_READ_OUT => buf_to_apl_INIT_READ,
+
+ -- Status and control port
+ -- not needed now, but later
+ );
+
+TERM_REPLY: trb_net_term
+
+ generic map (FIFO_TERM_BUFFER_DEPTH => 0)
+
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ -- "mini" APL, just to see the triggers coming in
+
+ APL_HOLD_TRM => '0',
+ APL_DTYPE_IN => (others => '0'),
+ APL_ERROR_PATTERN_IN => (others => '0'),
+
+ -- Internal direction port
+ -- connect via private signals
+
+ INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_REPLY_DATA,
+ INT_READ_IN => apl_to_buf_REPLY_READ,
+
+ INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+ INT_DATA_IN => buf_to_apl_REPLY_DATA,
+ INT_READ_OUT => buf_to_apl_REPLY_READ,
+
+ -- Status and control port
+ -- not needed now, but later
+ );
+
+IOBUF: trb_net_iobuf
+
+ generic map (INIT_DEPTH => 0,
+ REPLY_DEPTH => 0)
+
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
+ MED_INIT_READ_IN => MED_INIT_READ_IN,
+
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_INIT_DATA_IN,
+ MED_INIT_READ_OUT => MED_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
+ MED_REPLY_READ_IN => MED_REPLY_READ_IN,
+
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
+ MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ,
+
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
+
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
+
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
+
+ -- Status and control port
+ STAT_GEN => STAT_GEN,
+ STAT_LOCKED => STAT_LOCKED,
+ STAT_INIT_BUFFER => STAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_GEN,
+ CTRL_LOCKED => CTRL_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
+ );
+
+ MPLEX: trb_net_io_multiplexer
+ generic map (BUS_WIDTH => 52,
+ MULT_WIDTH => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET ,
+ CLK_EN => CLK_EN,
+
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_READ_OUT => MED_READ_OUT,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_READ_IN => MED_READ_IN,
+
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_READ_IN =>m_READ_OUT,
+
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_READ_OUT =>m_READ_IN,
+
+ CTRL => MPLEX_CTRL
+
+ );
+
+end trb_net_term_mbuf_arch;
+
jspc29 / trbnet.git / commitdiff