Added Strecher files, needed for internal delay. Optimized placement of Strecher...

diff --git a/amps/padiwa_amps.vhd b/amps/padiwa_amps.vhd
index 78613b7e6c7f227b6a07f54c5372245317e07a36..e119ee1892868e1f969aed27f75dea8a25c490a3 100644 (file)
--- a/amps/padiwa_amps.vhd
+++ b/amps/padiwa_amps.vhd
@@ -211,7 +211,7 @@ signal flash_busy    : std_logic;
 signal flash_err     : std_logic;
 
 signal inp_select    : integer range 0 to 31 := 0;
-signal inp_invert   : std_logic_vector(15 downto 0) := (others => '1');
+signal inp_invert   : std_logic_vector(15 downto 0) := x"aaaa"; --invert slow inputs only
 signal input_enable : std_logic_vector(15 downto 0);
 signal inp_status   : std_logic_vector(15 downto 0);
 signal led_status   : std_logic_vector(8  downto 0) := "100000000";
@@ -610,8 +610,9 @@ THE_STRETCHER : entity work.Stretcher
 -- Delay generation
 ---------------------------------------------------------------------------
 
---git delay
-------------
+--old delay generation
+----------------------
+----------------------
 --gen_discharge : for i in 1 to 8 generate
 --DISCHARGE(i) <= 'Z'                               when  discharge_highz(i) = '1' else
 --               (DELAY_C_IN(i) and slow_input(i)) when  discharge_disable(i) = '0' else
@@ -620,8 +621,9 @@ THE_STRETCHER : entity work.Stretcher
 --DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i);
 --end generate;
 
---delay intern: standard latch
--------------------------
+--new delay generation with internal delay
+------------------------------
+------------------------------
 gen_discharge : for i in 1 to 8 generate
 process (slow_input, selected_delay)
 begin
@@ -632,7 +634,6 @@ begin
    end if;
 end process;
 
--- delayed_inputs(i) <= selected_delay(i);
 selected_delay(i) <= delayed_inputs(i*DELAYDEPTH-1-delayselect);
 end generate;
 
@@ -671,8 +672,6 @@ inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold;
 
 
 
-
-
 SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)
   begin
     if inp_select < 16 then
@@ -694,6 +693,8 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
 --TEST_LINE(7 downto 0) <= delayed_inputs(7 downto 0);
 --TEST_LINE(8) <= fast_input(1);
 --TEST_LINE(13 downto 9) <= (others => '0');
+
+--Test lines for selected delay
 TEST_LINE(7 downto 0) <= selected_delay;
 
 gen_leds : for i in 1 to 8 generate
@@ -701,5 +702,4 @@ gen_leds : for i in 1 to 8 generate
 end generate;
 
 
-end architecture;
-
+end architecture;
\ No newline at end of file

diff --git a/pinout/padiwa_amps.lpf b/pinout/padiwa_amps.lpf
index 7dbbdd757c94c119a5d36018929347d84af38992..cf47556f37563fba62bc93bd9e2fc5ce3876328f 100644 (file)
--- a/pinout/padiwa_amps.lpf
+++ b/pinout/padiwa_amps.lpf
@@ -208,12 +208,12 @@ IOBUF GROUP  "DELAY_C_IN_group" IO_TYPE=LVCMOS33  ;
 UGROUP "StretchA" BBOX 8 2\r
   BLKNAME THE_STRETCHER/Stretcher_A_1\r
   ;\r
-LOCATE UGROUP "StretchA" SITE "R2C2D";  \r
+LOCATE UGROUP "StretchA" SITE "R13C2D";  \r
   \r
 UGROUP "StretchB" BBOX 8 2\r
   BLKNAME THE_STRETCHER/Stretcher_B_1\r
   ;\r
-LOCATE UGROUP "StretchB" SITE "R2C30D";  \r
+LOCATE UGROUP "StretchB" SITE "R13C30D";  \r
   \r
-\r
+MAXDELAY FROM PORT "INP[1]" TO CELL "gen_discharge.1.DISCHARGE[1]" 180 NS;\r
   
\ No newline at end of file

diff --git a/source/Stretcher.vhd b/source/Stretcher.vhd
new file mode 100644 (file)
index 0000000..5167ec3
--- /dev/null
+++ b/source/Stretcher.vhd
@@ -0,0 +1,64 @@
+-------------------------------------------------------------------------------
+-- Title      : Stretcher
+-- Project    : 
+-------------------------------------------------------------------------------
+-- File       : Stretcher.vhd
+-- Author     : cugur@gsi.de
+-- Created    : 2012-11-07
+-- Last update: 2016-01-20
+-------------------------------------------------------------------------------
+-- Description: Jan's counting
+-------------------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.tdc_components.all;
+
+entity Stretcher is
+  generic (
+    CHANNEL : integer range 1 to 64 := 1;
+    DEPTH   : integer range 1 to 32 := 3);
+  port (
+    PULSE_IN  : in  std_logic_vector(CHANNEL-1 downto 0);
+    PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));
+
+end Stretcher;
+
+architecture behavioral of Stretcher is
+
+  signal pulse_a_in  : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+  signal pulse_a_out : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+  signal pulse_b_in  : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+  signal pulse_b_out : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+
+begin  -- behavioral
+
+  GEN : for i in 0 to CHANNEL-1 generate
+    pulse_a_in(DEPTH*i+DEPTH-1)                <= PULSE_IN(i);
+    pulse_a_in(DEPTH*i+DEPTH-2 downto DEPTH*i) <= pulse_b_out(DEPTH*i+DEPTH-1 downto DEPTH*i+1);
+    pulse_b_in(DEPTH*i+DEPTH-1 downto DEPTH*i+1) <= pulse_a_out(DEPTH*i+DEPTH-1 downto DEPTH*i+1);
+--     PULSE_OUT(i-1)                             <= transport not pulse_a_out(DEPTH*(i-1)) after 42.186 ns;
+  end generate GEN;
+
+  PULSE_OUT <= pulse_b_out;
+
+  Stretcher_A_1 : entity work.Stretcher_A
+    generic map (
+      CHANNEL => CHANNEL,
+      DEPTH   => DEPTH)
+    port map (
+      PULSE_IN  => pulse_a_in,
+      PULSE_OUT => pulse_a_out);
+
+  Stretcher_B_1 : entity work.Stretcher_A
+    generic map (
+      CHANNEL => CHANNEL,
+      DEPTH   => DEPTH)
+    port map (
+      PULSE_IN  => pulse_b_in,
+      PULSE_OUT => pulse_b_out);
+
+end behavioral;

diff --git a/source/Stretcher_A.vhd b/source/Stretcher_A.vhd
new file mode 100644 (file)
index 0000000..335c123
--- /dev/null
+++ b/source/Stretcher_A.vhd
@@ -0,0 +1,49 @@
+-------------------------------------------------------------------------------
+-- Title      : Stretcher_A
+-- Project    : TRB3
+-------------------------------------------------------------------------------
+-- File       : Stretcher_A.vhd
+-- Author     : Cahit Ugur  <c.ugur@gsi.de>
+-- Created    : 2014-11-24
+-- Last update: 2016-01-20
+-------------------------------------------------------------------------------
+-- Description: Jan's counting
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2014-11-24  1.0      cugur   Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Stretcher_A is
+  generic (
+    CHANNEL : integer range 1 to 64;
+    DEPTH   : integer range 1 to 32 := 3);
+  port (
+    PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+    PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));
+
+end entity Stretcher_A;
+
+architecture behavioral of Stretcher_A is
+
+  signal pulse : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+
+  attribute syn_keep              : boolean;
+  attribute syn_keep of pulse     : signal is true;
+  attribute syn_preserve          : boolean;
+  attribute syn_preserve of pulse : signal is true;
+  attribute NOMERGE               : string;
+  attribute NOMERGE of pulse      : signal is "KEEP";
+
+begin  -- architecture behavioral
+
+  pulse     <= PULSE_IN;
+  PULSE_OUT <= not pulse;
+
+end architecture behavioral;

diff --git a/source/Stretcher_B.vhd b/source/Stretcher_B.vhd
new file mode 100644 (file)
index 0000000..a2d01aa
--- /dev/null
+++ b/source/Stretcher_B.vhd
@@ -0,0 +1,49 @@
+-------------------------------------------------------------------------------
+-- Title      : Stretcher_B
+-- Project    : TRB3
+-------------------------------------------------------------------------------
+-- File       : Stretcher_B.vhd
+-- Author     : Cahit Ugur  <c.ugur@gsi.de>
+-- Created    : 2014-11-24
+-- Last update: 2016-01-20
+-------------------------------------------------------------------------------
+-- Description: Jan's counting
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2014-11-24  1.0      cugur   Created
+-------------------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Stretcher_B is
+  generic (
+    CHANNEL : integer range 1 to 64;
+    DEPTH   : integer range 1 to 32 := 3);
+  port (
+    PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+    PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));
+
+end entity Stretcher_B;
+
+architecture behavioral of Stretcher_B is
+
+  signal pulse : std_logic_vector(CHANNEL*DEPTH-1 downto 0);
+
+  attribute syn_keep              : boolean;
+  attribute syn_keep of pulse     : signal is true;
+  attribute syn_preserve          : boolean;
+  attribute syn_preserve of pulse : signal is true;
+  attribute NOMERGE               : string;
+  attribute NOMERGE of pulse      : signal is "KEEP";
+
+begin  -- architecture behavioral
+
+  pulse     <= PULSE_IN;
+  PULSE_OUT <= not pulse;
+
+end architecture behavioral;