Starting standalone CFD processor

diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd
index 48dd60aab43897f409964f5a24ef887a1e738ea2..9e7e701e84e2c43f0dbbe1bc29c5a0a6a2b26513 100644 (file)
--- a/ADC/source/adc_package.vhd
+++ b/ADC/source/adc_package.vhd
@@ -25,7 +25,7 @@ type unsigned_array_8  is array (integer range <>) of unsigned( 7 downto 0);
 
 
 type cfg_t is record
-  processing_mode   : integer range 0 to 3; --0: normal block processing, 1: pulse shape processing, 2: CFD
+  processing_mode   : integer range 0 to 3; --0: normal block processing, 1: pulse shape processing
   buffer_depth      : unsigned(10 downto 0);
   samples_after     : unsigned(10 downto 0);
   block_count       : unsigned( 1 downto 0);
@@ -47,6 +47,18 @@ type cfg_t is record
   cfd_delay         : unsigned( 3 downto 0);
 end record;
 
+type cfg_cfd_t is record
+  InputThreshold   : unsigned(9 downto 0);
+  PolarityInvert   : std_logic;
+  BaselineAverage  : unsigned(3 downto 0);
+  BaselineAlwaysOn : std_logic;
+  CFDDelay         : unsigned(4 downto 0);
+  CFDMult          : unsigned(3 downto 0);
+  CFDMultDly       : unsigned(3 downto 0);
+  IntegrateWindow  : unsigned(7 downto 0);
+  TriggerDelay     : unsigned(11 downto 0);
+end record;
+
 end package;
 
 

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
new file mode 100644 (file)
index 0000000..5f5affb
--- /dev/null
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.trb_net_std.all;
+use work.trb3_components.all;
+use work.adc_package.all;
+
+entity adc_processor_cfd is
+  generic(
+    DEVICE : integer range 0 to 15 := 15
+  );
+  port(
+    CLK                : in  std_logic;
+
+    ADC_DATA           : in  std_logic_vector(RESOLUTION * CHANNELS - 1 downto 0);
+    STOP_IN            : in  std_logic;
+    TRIGGER_OUT        : out std_logic;
+
+    CONTROL            : in  std_logic_vector(63 downto 0);
+    CONFIG             : in  cfg_cfd_t;
+
+    DEBUG_BUFFER_READ  : in  std_logic;
+    DEBUG_BUFFER_ADDR  : in  std_logic_vector(4 downto 0);
+    DEBUG_BUFFER_DATA  : out std_logic_vector(31 downto 0);
+    DEBUG_BUFFER_READY : out std_logic;
+
+    READOUT_RX         : in  READOUT_RX;
+    READOUT_TX         : out READOUT_TX
+  );
+end entity adc_processor_cfd;
+
+architecture arch of adc_processor_cfd is
+  
+begin
+  
+end architecture arch;