-- the new FIFO interface
- -- 10: frame_start
- -- 9 : fifo_wr
- -- 8 : fifo_eof
- -- 7..0: fifo_data
- type dl_rx_data_t is array(0 to 0) of std_logic_vector(10 downto 0);
- signal dl_rx_data : dl_rx_data_t;
- signal dl_rx_frame_req : std_logic_vector(0 downto 0);
- signal dl_rx_frame_ack : std_logic_vector(0 downto 0);
- signal dl_rx_frame_avail : std_logic_vector(0 downto 0);
- signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
- signal dl_tx_fifofull : std_logic_vector(0 downto 0);
-
-- 10: frame_start
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: data
signal ul_rx_data : std_logic_vector(10 downto 0);
- signal ul_tx_data : std_logic_vector(10 downto 0);
- signal ul_tx_fifofull : std_logic;
signal ul_rx_frame_avail : std_logic;
signal ul_rx_frame_req : std_logic;
signal ul_rx_frame_ack : std_logic;
signal ul_rx_fifofull : std_logic;
+ signal ul_tx_data : std_logic_vector(10 downto 0);
+ signal ul_tx_fifofull : std_logic;
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: fifo_data
+ type dl_rx_data_t is array(0 to 1) of std_logic_vector(10 downto 0);
+ signal dl_rx_data : dl_rx_data_t;
+ signal dl_rx_frame_req : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_ack : std_logic_vector(1 downto 0);
+ signal dl_rx_frame_avail : std_logic_vector(1 downto 0);
+ signal dl_rx_fifofull : std_logic_vector(1 downto 0);
+ signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
+ signal dl_tx_fifofull : std_logic_vector(1 downto 0);
-- 10: frame_start
-- 9 : fifo_wr
signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
- signal dl_rx_port_sel : std_logic_vector(0 downto 0);
+ signal dl_rx_port_sel : std_logic_vector(1 downto 0);
+ signal dl_rx_port_mux : std_logic_vector(3 downto 0);
signal ul_tx_port_sel : std_logic;
signal dl_tx_port_sel : std_logic;
signal local_tx_port_sel : std_logic;
---------------------------------------------------------------------------
--- GbE interface
+-- GbE interface (SFP)
---------------------------------------------------------------------------
- GBE_MED_INTERFACE: entity gbe_med_fifo
+ GBE_SFP_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 0
+ SERDES_NUM => 3
)
port map(
RESET => reset_i,
MAC_RX_ERROR_OUT => sniffer_error,
-- Status
PCS_AN_READY_OUT => open,
- LINK_ACTIVE_OUT => link_active,
+ LINK_ACTIVE_OUT => link_active, -- only needed on UL port for SCTRL
TICK_MS_IN => tick_ms_int,
-- Debug
STATUS_OUT => status(7 downto 0),
- DEBUG_OUT => open --debug(63 downto 0)
+-- DEBUG_OUT => open
+ DEBUG_OUT(9 downto 0) => debug(9 downto 0),
+ DEBUG_OUT(13 downto 10) => debug(23 downto 20)
);
---------------------------------------------------------------------------
+-- GbE interface (copper)
---------------------------------------------------------------------------
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
+ GBE_COPPER_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 0
+ )
+ port map(
+ RESET => reset_i,
+ RESET_N => reset_n_i,
+ CLEAR => clear_i,
+ CLEAR_N => clear_n_i,
+ CLK_125 => clk_sys,
+ -- FIFO interface RX
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
+ FIFO_WR_OUT => dl_rx_data(1)(9),
+ FIFO_DATA_OUT => dl_rx_data(1)(8 downto 0),
+ FRAME_START_OUT => dl_rx_data(1)(10),
+ FRAME_REQ_IN => dl_rx_frame_req(1),
+ FRAME_ACK_OUT => dl_rx_frame_ack(1),
+ FRAME_AVAIL_OUT => dl_rx_frame_avail(1),
+ -- FIFO interface TX
+ FIFO_WR_IN => dl_tx_data(9),
+ FIFO_DATA_IN => dl_tx_data(8 downto 0),
+ FRAME_START_IN => dl_tx_data(10),
+ FIFO_FULL_OUT => dl_tx_fifofull(1),
+ --SFP Connection
+ SD_PRSNT_N_IN => '0',
+ SD_LOS_IN => '0',
+ SD_TXDIS_OUT => open,
+ -- internal sniffer port
+ -- Status
+ PCS_AN_READY_OUT => open,
+ LINK_ACTIVE_OUT => open,
+ TICK_MS_IN => tick_ms_int,
+ -- Debug
+ STATUS_OUT => open,
+-- DEBUG_OUT => open
+ DEBUG_OUT(9 downto 0) => debug(19 downto 10),
+ DEBUG_OUT(13 downto 10) => debug(27 downto 24)
+ );
+
+-- debug(19 downto 10) <= (others => '0');
+
+ debug(32 downto 28) <= (others => '0');
- debug(0) <= ul_rx_frame_avail;
- debug(1) <= ul_rx_frame_req;
- debug(2) <= ul_rx_frame_ack;
- debug(3) <= ul_tx_fifofull;
- debug(4) <= dl_rx_frame_avail(0);
- debug(5) <= dl_rx_frame_req(0);
- debug(6) <= dl_rx_frame_ack(0);
- debug(7) <= ul_rx_data(9);
- debug(8) <= ul_rx_data(10);
- debug(9) <= ul_tx_data(9);
- debug(10) <= ul_tx_data(10);
- debug(11) <= dl_rx_port_sel(0);
- debug(12) <= dl_tx_port_sel;
- debug(13) <= local_tx_port_sel;
- debug(14) <= ul_tx_port_sel;
- debug(15) <= '0';
- debug(19 downto 16) <= sgl_debug(3 downto 0);
- debug(20) <= '0';
- debug(21) <= '0';
- debug(22) <= '0';
- debug(23) <= '0';
- debug(24) <= '0';
- debug(25) <= '0';
- debug(26) <= '0';
- debug(27) <= '0';
- debug(28) <= '0';
- debug(29) <= '0';
- debug(30) <= '0';
- debug(31) <= '0';
- debug(32) <= '0';
debug(33) <= clk_sys;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
-- DL ports (includes SCTRL)
- DL_FIFOFULL_IN(0 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
- DL_FRAME_AVAIL_IN(0 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
- DL_FRAME_REQ_OUT(0 downto 0) => dl_rx_frame_req, -- DL RXn request to send
- DL_FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
+ DL_FIFOFULL_IN(1 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
+ DL_FRAME_AVAIL_IN(1 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
+ DL_FRAME_REQ_OUT(1 downto 0) => dl_rx_frame_req, -- DL RXn request to send
+ DL_FRAME_ACK_IN(1 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
-- CPU port -- not needed
-- MUX control
- DL_RX_PORT_SEL_OUT(0 downto 0) => dl_rx_port_sel,
- DL_RX_PORT_MUX_OUT => open,
+ DL_RX_PORT_SEL_OUT(1 downto 0) => dl_rx_port_sel,
+ DL_RX_PORT_MUX_OUT => dl_rx_port_mux,
DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
THE_DL_RX_MUX: process( dl_rx_port_sel, dl_rx_data )
begin
case dl_rx_port_sel is
- when b"1" => switch_rx_data <= dl_rx_data(0);
+ when b"01" => switch_rx_data <= dl_rx_data(0);
+ when b"10" => switch_rx_data <= dl_rx_data(1);
when others => switch_rx_data <= (others => '0');
end case;
end process THE_DL_RX_MUX;
dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; -- not needed
--- -- scattering: data from uplink is distributed to downlinks
--- THE_SCATTER: entity scatter_ports
--- port map(
--- CLK => clk_sys,
--- RESET => reset_i,
--- --
----- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0), -- not needed, only SCTRL at the moment
--- FIFO_FULL_OUT => ul_rx_fifofull,
--- FRAME_AVAIL_IN => ul_rx_frame_avail,
--- FRAME_REQ_OUT => ul_rx_frame_req,
--- FRAME_ACK_IN => ul_rx_frame_ack,
--- CYCLE_DONE_OUT => open,
--- --
--- DEBUG => open
--- );
---
--- THE_GATHER: entity gather_ports
--- port map(
--- CLK => clk_sys,
--- RESET => reset_i,
--- --
--- FRAME_AVAIL_IN(0 downto 0) => dl_rx_frame_avail(0 downto 0),
--- FRAME_REQ_OUT(0 downto 0) => dl_rx_frame_req(0 downto 0),
--- FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack(0 downto 0),
--- PORT_SELECT_OUT(0 downto 0) => port_sel,
--- PORT_MUX_OUT => open,
--- CYCLE_DONE_OUT => open,
--- --
--- DEBUG => open
--- );
---
--- THE_QUICK_MUX: process( port_sel, dl_rx_data )
--- begin
--- case port_sel is
--- when b"1" => ul_tx_data <= dl_rx_data(0);
--- when others => ul_tx_data <= (others => '0');
--- end case;
--- end process THE_QUICK_MUX;
---
--- ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
-
---------------------------------------------------------------------------
-- GbE wrapper without med interface
---------------------------------------------------------------------------
MAKE_RESET_OUT => reset_via_gbe,
-- debug
STATUS_OUT => status(15 downto 8),
- DEBUG_OUT => open --debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
+ DEBUG_OUT => open
);
THE_FWD_TEST: entity fwd_test_random
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
LED(3) <= not additional_reg(7); --'0';
- LED(2) <= not '1'; --additional_reg(6); --'0';
- LED(1) <= not additional_reg(5); --'0';
- LED(0) <= not additional_reg(4); --'0';
+ LED(2) <= not additional_reg(6); --'0';
+ LED(1) <= not '1'; --additional_reg(5); --'0';
+ LED(0) <= not '1'; --additional_reg(4); --'0';
-- 0 red
-- 1 orange