\end{warning}
\subsection{Design Identification}
-The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules: The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and have to contain one of the following values:
+The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules:
+The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and
+have to contain one of the following values. The last digit should be used to denote the hardware revision.
\begin{description*}
\item[9000] design is for the central FPGA
\item[9100] design is for either of the peripheral FPGAs
\item[9500] design for Trb3sc
\item[9600] design for DiRich
\item[9700] design for DiRich Combiner module
+ \item[9900] design for Munich Skyroc boards
\end{description*}
The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine