library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_med_ecp_fot_4 is
+ generic(
+ REVERSE_ORDER : integer range 0 to 1 := c_NO
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
+ );
port(
CLK : in std_logic;
CLK_25 : in std_logic;
);
end component;
- component trb_net16_lsm_sfp is
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available
- -- status signals
- SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)
- SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)
- SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)
- -- control signals
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset
- TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation
- RX_ALLOW_OUT : out std_logic; -- allow normal receive operation
- SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)
- -- debug signals
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
- );
- end component;
component lattice_ecp2m_fifo_8x8_dualport
port (
);
end component;
+
component lattice_ecp2m_fifo_16x8_dualport
port (
Data: in std_logic_vector(15 downto 0);
);
end component;
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port( read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
- );
- end component;
type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0);
signal link_error : link_error_t;
attribute syn_keep of led_counter : signal is true;
begin
+ gen_normal_serdes : if REVERSE_ORDER = c_NO generate
+ THE_SERDES: serdes_fot_full_quad
+ port map(
+ core_txrefclk => CLK_25,
+ core_rxrefclk => CLK_25,
+ hdinp0 => RXP(0),
+ hdinn0 => RXN(0),
+ hdoutp0 => TXP(0),
+ hdoutn0 => TXN(0),
+ ff_rxiclk_ch0 => ff_rxfullclk(0),
+ ff_txiclk_ch0 => ff_txfullclk,
+ ff_ebrd_clk_0 => ff_rxfullclk(0),
+ ff_txdata_ch0 => tx_data(7 downto 0),
+ ff_rxdata_ch0 => rx_data(7 downto 0),
+ ff_tx_k_cntrl_ch0 => tx_k(0),
+ ff_rx_k_cntrl_ch0 => rx_k(0),
+ ff_rxfullclk_ch0 => ff_rxfullclk(0),
+ ff_force_disp_ch0 => '0',
+ ff_disp_sel_ch0 => '0',
+ ff_correct_disp_ch0 => '0',
+ ff_disp_err_ch0 => link_error(0)(0),
+ ff_cv_ch0 => link_error(0)(1),
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => lane_rst(0), --lane_rst(0),
+ ffc_lane_rx_rst_ch0 => lane_rst(0),
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffs_rlos_lo_ch0 => link_error(0)(2),
+ ffs_ls_sync_status_ch0 => link_ok(0),
+ ffs_cc_underrun_ch0 => link_error(0)(3),
+ ffs_cc_overrun_ch0 => link_error(0)(4),
+ ffs_txfbfifo_error_ch0 => link_error(0)(5),
+ ffs_rxfbfifo_error_ch0 => link_error(0)(6),
+ ffs_rlol_ch0 => link_error(0)(7),
+ oob_out_ch0 => open,
+
+ hdinp1 => rxp(1),
+ hdinn1 => rxn(1),
+ hdoutp1 => txp(1),
+ hdoutn1 => txn(1),
+ ff_rxiclk_ch1 => ff_rxfullclk(1),
+ ff_txiclk_ch1 => ff_txfullclk,
+ ff_ebrd_clk_1 => ff_rxfullclk(1),
+ ff_txdata_ch1 => tx_data(15 downto 8),
+ ff_rxdata_ch1 => rx_data(15 downto 8),
+ ff_tx_k_cntrl_ch1 => tx_k(1),
+ ff_rx_k_cntrl_ch1 => rx_k(1),
+ ff_rxfullclk_ch1 => ff_rxfullclk(1),
+ ff_force_disp_ch1 => '0',
+ ff_disp_sel_ch1 => '0',
+ ff_correct_disp_ch1 => '0',
+ ff_disp_err_ch1 => link_error(1)(0),
+ ff_cv_ch1 => link_error(1)(1),
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => lane_rst(1), --lane_rst(1),
+ ffc_lane_rx_rst_ch1 => lane_rst(1),
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffs_rlos_lo_ch1 => link_error(1)(2),
+ ffs_ls_sync_status_ch1 => link_ok(1),
+ ffs_cc_underrun_ch1 => link_error(1)(3),
+ ffs_cc_overrun_ch1 => link_error(1)(4),
+ ffs_txfbfifo_error_ch1 => link_error(1)(5),
+ ffs_rxfbfifo_error_ch1 => link_error(1)(6),
+ ffs_rlol_ch1 => link_error(1)(7),
+ oob_out_ch1 => open,
+
+ hdinp2 => rxp(2),
+ hdinn2 => rxn(2),
+ hdoutp2 => txp(2),
+ hdoutn2 => txn(2),
+ ff_rxiclk_ch2 => ff_rxfullclk(2),
+ ff_txiclk_ch2 => ff_txfullclk,
+ ff_ebrd_clk_2 => ff_rxfullclk(2),
+ ff_txdata_ch2 => tx_data(23 downto 16),
+ ff_rxdata_ch2 => rx_data(23 downto 16),
+ ff_tx_k_cntrl_ch2 => tx_k(2),
+ ff_rx_k_cntrl_ch2 => rx_k(2),
+ ff_rxfullclk_ch2 => ff_rxfullclk(2),
+ ff_force_disp_ch2 => '0',
+ ff_disp_sel_ch2 => '0',
+ ff_correct_disp_ch2 => '0',
+ ff_disp_err_ch2 => link_error(2)(0),
+ ff_cv_ch2 => link_error(2)(1),
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => lane_rst(2), --lane_rst(2),
+ ffc_lane_rx_rst_ch2 => lane_rst(2),
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffs_rlos_lo_ch2 => link_error(2)(2),
+ ffs_ls_sync_status_ch2 => link_ok(2),
+ ffs_cc_underrun_ch2 => link_error(2)(3),
+ ffs_cc_overrun_ch2 => link_error(2)(4),
+ ffs_txfbfifo_error_ch2 => link_error(2)(5),
+ ffs_rxfbfifo_error_ch2 => link_error(2)(6),
+ ffs_rlol_ch2 => link_error(2)(7),
+ oob_out_ch2 => open,
+
+ hdinp3 => rxp(3),
+ hdinn3 => rxn(3),
+ hdoutp3 => txp(3),
+ hdoutn3 => txn(3),
+ ff_rxiclk_ch3 => ff_rxfullclk(3),
+ ff_txiclk_ch3 => ff_txfullclk,
+ ff_ebrd_clk_3 => ff_rxfullclk(3),
+ ff_txdata_ch3 => tx_data(31 downto 24),
+ ff_rxdata_ch3 => rx_data(31 downto 24),
+ ff_tx_k_cntrl_ch3 => tx_k(3),
+ ff_rx_k_cntrl_ch3 => rx_k(3),
+ ff_rxfullclk_ch3 => ff_rxfullclk(3),
+ ff_force_disp_ch3 => '0',
+ ff_disp_sel_ch3 => '0',
+ ff_correct_disp_ch3 => '0',
+ ff_disp_err_ch3 => link_error(3)(0),
+ ff_cv_ch3 => link_error(3)(1),
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => lane_rst(3), --lane_rst(3),
+ ffc_lane_rx_rst_ch3 => lane_rst(3),
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffs_rlos_lo_ch3 => link_error(3)(2),
+ ffs_ls_sync_status_ch3 => link_ok(3),
+ ffs_cc_underrun_ch3 => link_error(3)(3),
+ ffs_cc_overrun_ch3 => link_error(3)(4),
+ ffs_txfbfifo_error_ch3 => link_error(3)(5),
+ ffs_rxfbfifo_error_ch3 => link_error(3)(6),
+ ffs_rlol_ch3 => link_error(3)(7),
+ oob_out_ch3 => open,
+
+ ffc_macro_rst => '0',
+ ffc_quad_rst => quad_rst(0),
+ ffc_trst => '0',
+ ff_txfullclk => ff_txfullclk,
+ ffs_plol => ffs_plol
+ );
+ end generate;
- THE_SERDES: serdes_fot_full_quad
- port map(
- core_txrefclk => CLK_25,
- core_rxrefclk => CLK_25,
- hdinp0 => RXP(0),
- hdinn0 => RXN(0),
- hdoutp0 => TXP(0),
- hdoutn0 => TXN(0),
- ff_rxiclk_ch0 => ff_rxfullclk(0),
- ff_txiclk_ch0 => ff_txfullclk,
- ff_ebrd_clk_0 => ff_rxfullclk(0),
- ff_txdata_ch0 => tx_data(7 downto 0),
- ff_rxdata_ch0 => rx_data(7 downto 0),
- ff_tx_k_cntrl_ch0 => tx_k(0),
- ff_rx_k_cntrl_ch0 => rx_k(0),
- ff_rxfullclk_ch0 => ff_rxfullclk(0),
- ff_force_disp_ch0 => '0',
- ff_disp_sel_ch0 => '0',
- ff_correct_disp_ch0 => '0',
- ff_disp_err_ch0 => link_error(0)(0),
- ff_cv_ch0 => link_error(0)(1),
- ffc_rrst_ch0 => '0',
- ffc_lane_tx_rst_ch0 => lane_rst(0), --lane_rst(0),
- ffc_lane_rx_rst_ch0 => lane_rst(0),
- ffc_txpwdnb_ch0 => '1',
- ffc_rxpwdnb_ch0 => '1',
- ffs_rlos_lo_ch0 => link_error(0)(2),
- ffs_ls_sync_status_ch0 => link_ok(0),
- ffs_cc_underrun_ch0 => link_error(0)(3),
- ffs_cc_overrun_ch0 => link_error(0)(4),
- ffs_txfbfifo_error_ch0 => link_error(0)(5),
- ffs_rxfbfifo_error_ch0 => link_error(0)(6),
- ffs_rlol_ch0 => link_error(0)(7),
- oob_out_ch0 => open,
-
- hdinp1 => rxp(1),
- hdinn1 => rxn(1),
- hdoutp1 => txp(1),
- hdoutn1 => txn(1),
- ff_rxiclk_ch1 => ff_rxfullclk(1),
- ff_txiclk_ch1 => ff_txfullclk,
- ff_ebrd_clk_1 => ff_rxfullclk(1),
- ff_txdata_ch1 => tx_data(15 downto 8),
- ff_rxdata_ch1 => rx_data(15 downto 8),
- ff_tx_k_cntrl_ch1 => tx_k(1),
- ff_rx_k_cntrl_ch1 => rx_k(1),
- ff_rxfullclk_ch1 => ff_rxfullclk(1),
- ff_force_disp_ch1 => '0',
- ff_disp_sel_ch1 => '0',
- ff_correct_disp_ch1 => '0',
- ff_disp_err_ch1 => link_error(1)(0),
- ff_cv_ch1 => link_error(1)(1),
- ffc_rrst_ch1 => '0',
- ffc_lane_tx_rst_ch1 => lane_rst(1), --lane_rst(1),
- ffc_lane_rx_rst_ch1 => lane_rst(1),
- ffc_txpwdnb_ch1 => '1',
- ffc_rxpwdnb_ch1 => '1',
- ffs_rlos_lo_ch1 => link_error(1)(2),
- ffs_ls_sync_status_ch1 => link_ok(1),
- ffs_cc_underrun_ch1 => link_error(1)(3),
- ffs_cc_overrun_ch1 => link_error(1)(4),
- ffs_txfbfifo_error_ch1 => link_error(1)(5),
- ffs_rxfbfifo_error_ch1 => link_error(1)(6),
- ffs_rlol_ch1 => link_error(1)(7),
- oob_out_ch1 => open,
-
- hdinp2 => rxp(2),
- hdinn2 => rxn(2),
- hdoutp2 => txp(2),
- hdoutn2 => txn(2),
- ff_rxiclk_ch2 => ff_rxfullclk(2),
- ff_txiclk_ch2 => ff_txfullclk,
- ff_ebrd_clk_2 => ff_rxfullclk(2),
- ff_txdata_ch2 => tx_data(23 downto 16),
- ff_rxdata_ch2 => rx_data(23 downto 16),
- ff_tx_k_cntrl_ch2 => tx_k(2),
- ff_rx_k_cntrl_ch2 => rx_k(2),
- ff_rxfullclk_ch2 => ff_rxfullclk(2),
- ff_force_disp_ch2 => '0',
- ff_disp_sel_ch2 => '0',
- ff_correct_disp_ch2 => '0',
- ff_disp_err_ch2 => link_error(2)(0),
- ff_cv_ch2 => link_error(2)(1),
- ffc_rrst_ch2 => '0',
- ffc_lane_tx_rst_ch2 => lane_rst(2), --lane_rst(2),
- ffc_lane_rx_rst_ch2 => lane_rst(2),
- ffc_txpwdnb_ch2 => '1',
- ffc_rxpwdnb_ch2 => '1',
- ffs_rlos_lo_ch2 => link_error(2)(2),
- ffs_ls_sync_status_ch2 => link_ok(2),
- ffs_cc_underrun_ch2 => link_error(2)(3),
- ffs_cc_overrun_ch2 => link_error(2)(4),
- ffs_txfbfifo_error_ch2 => link_error(2)(5),
- ffs_rxfbfifo_error_ch2 => link_error(2)(6),
- ffs_rlol_ch2 => link_error(2)(7),
- oob_out_ch2 => open,
-
- hdinp3 => rxp(3),
- hdinn3 => rxn(3),
- hdoutp3 => txp(3),
- hdoutn3 => txn(3),
- ff_rxiclk_ch3 => ff_rxfullclk(3),
- ff_txiclk_ch3 => ff_txfullclk,
- ff_ebrd_clk_3 => ff_rxfullclk(3),
- ff_txdata_ch3 => tx_data(31 downto 24),
- ff_rxdata_ch3 => rx_data(31 downto 24),
- ff_tx_k_cntrl_ch3 => tx_k(3),
- ff_rx_k_cntrl_ch3 => rx_k(3),
- ff_rxfullclk_ch3 => ff_rxfullclk(3),
- ff_force_disp_ch3 => '0',
- ff_disp_sel_ch3 => '0',
- ff_correct_disp_ch3 => '0',
- ff_disp_err_ch3 => link_error(3)(0),
- ff_cv_ch3 => link_error(3)(1),
- ffc_rrst_ch3 => '0',
- ffc_lane_tx_rst_ch3 => lane_rst(3), --lane_rst(3),
- ffc_lane_rx_rst_ch3 => lane_rst(3),
- ffc_txpwdnb_ch3 => '1',
- ffc_rxpwdnb_ch3 => '1',
- ffs_rlos_lo_ch3 => link_error(3)(2),
- ffs_ls_sync_status_ch3 => link_ok(3),
- ffs_cc_underrun_ch3 => link_error(3)(3),
- ffs_cc_overrun_ch3 => link_error(3)(4),
- ffs_txfbfifo_error_ch3 => link_error(3)(5),
- ffs_rxfbfifo_error_ch3 => link_error(3)(6),
- ffs_rlol_ch3 => link_error(3)(7),
- oob_out_ch3 => open,
-
- ffc_macro_rst => '0',
- ffc_quad_rst => quad_rst(0),
- ffc_trst => '0',
- ff_txfullclk => ff_txfullclk,
- ffs_plol => ffs_plol
- );
+ gen_twisted_serdes : if REVERSE_ORDER = c_YES generate
+ THE_SERDES: serdes_fot_full_quad
+ port map(
+ core_txrefclk => CLK_25,
+ core_rxrefclk => CLK_25,
+ hdinp0 => RXP(0),
+ hdinn0 => RXN(0),
+ hdoutp0 => TXP(0),
+ hdoutn0 => TXN(0),
+ ff_rxiclk_ch0 => ff_rxfullclk(3),
+ ff_txiclk_ch0 => ff_txfullclk,
+ ff_ebrd_clk_0 => ff_rxfullclk(3),
+ ff_txdata_ch0 => tx_data(31 downto 24),
+ ff_rxdata_ch0 => rx_data(31 downto 24),
+ ff_tx_k_cntrl_ch0 => tx_k(3),
+ ff_rx_k_cntrl_ch0 => rx_k(3),
+ ff_rxfullclk_ch0 => ff_rxfullclk(3),
+ ff_force_disp_ch0 => '0',
+ ff_disp_sel_ch0 => '0',
+ ff_correct_disp_ch0 => '0',
+ ff_disp_err_ch0 => link_error(3)(0),
+ ff_cv_ch0 => link_error(3)(1),
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => lane_rst(3), --lane_rst(0),
+ ffc_lane_rx_rst_ch0 => lane_rst(3),
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffs_rlos_lo_ch0 => link_error(3)(2),
+ ffs_ls_sync_status_ch0 => link_ok(3),
+ ffs_cc_underrun_ch0 => link_error(3)(3),
+ ffs_cc_overrun_ch0 => link_error(3)(4),
+ ffs_txfbfifo_error_ch0 => link_error(3)(5),
+ ffs_rxfbfifo_error_ch0 => link_error(3)(6),
+ ffs_rlol_ch0 => link_error(3)(7),
+ oob_out_ch0 => open,
+
+ hdinp1 => rxp(1),
+ hdinn1 => rxn(1),
+ hdoutp1 => txp(1),
+ hdoutn1 => txn(1),
+ ff_rxiclk_ch1 => ff_rxfullclk(2),
+ ff_txiclk_ch1 => ff_txfullclk,
+ ff_ebrd_clk_1 => ff_rxfullclk(2),
+ ff_txdata_ch1 => tx_data(23 downto 16),
+ ff_rxdata_ch1 => rx_data(23 downto 16),
+ ff_tx_k_cntrl_ch1 => tx_k(2),
+ ff_rx_k_cntrl_ch1 => rx_k(2),
+ ff_rxfullclk_ch1 => ff_rxfullclk(2),
+ ff_force_disp_ch1 => '0',
+ ff_disp_sel_ch1 => '0',
+ ff_correct_disp_ch1 => '0',
+ ff_disp_err_ch1 => link_error(2)(0),
+ ff_cv_ch1 => link_error(2)(1),
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => lane_rst(2), --lane_rst(1),
+ ffc_lane_rx_rst_ch1 => lane_rst(2),
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffs_rlos_lo_ch1 => link_error(2)(2),
+ ffs_ls_sync_status_ch1 => link_ok(2),
+ ffs_cc_underrun_ch1 => link_error(2)(3),
+ ffs_cc_overrun_ch1 => link_error(2)(4),
+ ffs_txfbfifo_error_ch1 => link_error(2)(5),
+ ffs_rxfbfifo_error_ch1 => link_error(2)(6),
+ ffs_rlol_ch1 => link_error(2)(7),
+ oob_out_ch1 => open,
+
+ hdinp2 => rxp(2),
+ hdinn2 => rxn(2),
+ hdoutp2 => txp(2),
+ hdoutn2 => txn(2),
+ ff_rxiclk_ch2 => ff_rxfullclk(1),
+ ff_txiclk_ch2 => ff_txfullclk,
+ ff_ebrd_clk_2 => ff_rxfullclk(1),
+ ff_txdata_ch2 => tx_data(15 downto 8),
+ ff_rxdata_ch2 => rx_data(15 downto 8),
+ ff_tx_k_cntrl_ch2 => tx_k(1),
+ ff_rx_k_cntrl_ch2 => rx_k(1),
+ ff_rxfullclk_ch2 => ff_rxfullclk(1),
+ ff_force_disp_ch2 => '0',
+ ff_disp_sel_ch2 => '0',
+ ff_correct_disp_ch2 => '0',
+ ff_disp_err_ch2 => link_error(1)(0),
+ ff_cv_ch2 => link_error(1)(1),
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => lane_rst(1), --lane_rst(2),
+ ffc_lane_rx_rst_ch2 => lane_rst(1),
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffs_rlos_lo_ch2 => link_error(1)(2),
+ ffs_ls_sync_status_ch2 => link_ok(1),
+ ffs_cc_underrun_ch2 => link_error(1)(3),
+ ffs_cc_overrun_ch2 => link_error(1)(4),
+ ffs_txfbfifo_error_ch2 => link_error(1)(5),
+ ffs_rxfbfifo_error_ch2 => link_error(1)(6),
+ ffs_rlol_ch2 => link_error(1)(7),
+ oob_out_ch2 => open,
+
+ hdinp3 => rxp(3),
+ hdinn3 => rxn(3),
+ hdoutp3 => txp(3),
+ hdoutn3 => txn(3),
+ ff_rxiclk_ch3 => ff_rxfullclk(0),
+ ff_txiclk_ch3 => ff_txfullclk,
+ ff_ebrd_clk_3 => ff_rxfullclk(0),
+ ff_txdata_ch3 => tx_data(7 downto 0),
+ ff_rxdata_ch3 => rx_data(7 downto 0),
+ ff_tx_k_cntrl_ch3 => tx_k(0),
+ ff_rx_k_cntrl_ch3 => rx_k(0),
+ ff_rxfullclk_ch3 => ff_rxfullclk(0),
+ ff_force_disp_ch3 => '0',
+ ff_disp_sel_ch3 => '0',
+ ff_correct_disp_ch3 => '0',
+ ff_disp_err_ch3 => link_error(0)(0),
+ ff_cv_ch3 => link_error(0)(1),
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => lane_rst(0), --lane_rst(3),
+ ffc_lane_rx_rst_ch3 => lane_rst(0),
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffs_rlos_lo_ch3 => link_error(0)(2),
+ ffs_ls_sync_status_ch3 => link_ok(0),
+ ffs_cc_underrun_ch3 => link_error(0)(3),
+ ffs_cc_overrun_ch3 => link_error(0)(4),
+ ffs_txfbfifo_error_ch3 => link_error(0)(5),
+ ffs_rxfbfifo_error_ch3 => link_error(0)(6),
+ ffs_rlol_ch3 => link_error(0)(7),
+ oob_out_ch3 => open,
+
+ ffc_macro_rst => '0',
+ ffc_quad_rst => quad_rst(0),
+ ffc_trst => '0',
+ ff_txfullclk => ff_txfullclk,
+ ffs_plol => ffs_plol
+ );
+ end generate;
--TX Control 25
---------------
USE_STATUS_FLAGS => c_NO
)
port map(
- read_clock_in => ff_txfullclk,
+ read_clock_in => ff_txfullclk,
write_clock_in => CLK,
read_enable_in => tx_fifo_read_en(i),
- write_enable_in => tx_fifo_write_en(i),
- fifo_gsr_in => fifo_reset(i),
- write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16),
+ write_enable_in => tx_fifo_write_en(i),
+ fifo_gsr_in => fifo_reset(i),
+ write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16),
read_data_out(15 downto 0) => tx_fifo_dout((i+1)*16-1 downto i*16),
- full_out => tx_fifo_full(i),
- empty_out => tx_fifo_empty(i)
+ full_out => tx_fifo_full(i),
+ empty_out => tx_fifo_empty(i)
);
-- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_med_ecp_sfp_4 is
generic(
);
end component;
- component trb_net16_lsm_sfp is
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available
- -- status signals
- SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)
- SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)
- SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)
- -- control signals
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset
- TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation
- RX_ALLOW_OUT : out std_logic; -- allow normal receive operation
- SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)
- -- debug signals
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port( read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
- );
- end component;
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
- );
- end component;
type link_error_t is array(0 to 3) of std_logic_vector(9 downto 0);
--------------------------------------------------------------------------
gen_reset_i : for i in 0 to 3 generate
- reset_i(i) <= RESET or CTRL_OP(i*16+14);
- pwr_up(i) <= not CTRL_OP(i*16+14);
+ PROC_RESET : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ reset_i(i) <= RESET or CTRL_OP(i*16+14);
+ pwr_up(i) <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+ end process;
end generate;
+
+IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
#################################################################
# Clock I/O
#################################################################
signal m_DATA_IN : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal m_ERROR_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*3-1 downto 0);
+ signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0);
signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0);
signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
signal HC_CTRL_REGS : std_logic_vector (2**3*32-1 downto 0);
signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal buf_HC_STAT_REGS : std_logic_vector (2**3*32-1 downto 0);
signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
);
end generate;
gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate
+ hub_to_buf_init_read(i) <= '0';
+ buf_to_hub_init_dataready(i) <= '0';
+ buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_to_hub_init_packet_num((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ hub_to_buf_reply_read(i) <= '0';
+ buf_to_hub_reply_dataready(i) <= '0';
+ buf_to_hub_reply_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+ buf_to_hub_reply_packet_num((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+ iobuf_stat_gen((i+1)*32-1 downto i*32) <= (others => '0');
+ IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
+ IOBUF_CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0');
+ IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+ IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+
+
IOBUF : trb_net16_term_buf
port map (
-- Misc
);
buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
end generate;
+ gen_select_no_logic : if i = 2 generate
+ buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
+ HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
+ HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
+ HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
+ HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
+ HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_INIT_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
+ end generate;
end generate;
end generate;
HC_COMMON_STAT_REGS(63 downto 32) <= (others => '0');
--Status Registers
- HC_STAT_REGS(2**(c_MUX_WIDTH-1)*32-1 downto 0) <= buf_STAT_POINTS_locked;
- HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED;
- HC_STAT_REGS(8*32-1 downto 5*32) <= (others => '0'); --unused regs
+ buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked;
+ buf_HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED;
+ buf_HC_STAT_REGS(8*32-1 downto 5*32) <= (others => '0'); --unused regs
+
+ PROC_LED : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ HC_STAT_REGS <= buf_HC_STAT_REGS;
+ end if;
+ end process;
--Control Registers
HUB_CTRL_activepoints <= HC_CTRL_REGS(2**2*32-1 downto 0);
package trb_net16_hub_func is
--type for hub arrays
- type hub_iobuf_config_t is array(0 to 63) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1
+ type hub_iobuf_config_t is array(0 to 67) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1
type hub_api_config_t is array(0 to 7) of integer;
type hub_api_broadcast_t is array(0 to 7) of std_logic_vector(7 downto 0);
type hub_channel_config_t is array(0 to 2**(3-1)-1) of integer;
type hub_mii_config_t is array(0 to 16) of integer;
--hub constraints (only needed for generic configuration)
- constant c_MAX_MII_PER_HUB : integer := 16;
+ constant c_MAX_MII_PER_HUB : integer := 17;
constant c_MAX_API_PER_HUB : integer := 8;
constant c_MAX_TRG_PER_HUB : integer := 8;
constant c_MAX_POINTS_PER_HUB : integer := 18;
1,6,6,6,
1,6,6,6,
1,6,6,6,
+ 1,6,6,6,
1,6,6,6); --MII 15
constant std_hub_mii_all_yes : hub_mii_config_t := (c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,
INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
signal current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal current_reply_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_muxed_reading_DAT : std_logic;
signal next_last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
signal current_point_length : unsigned(15 downto 0);
- signal reply_mux_number : integer range 0 to POINT_NUMBER-1;
signal start_read_padding : std_logic_vector(POINT_NUMBER-1 downto 0);
signal saved_reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0);
gen_read_out : for i in 0 to POINT_NUMBER-1 generate
buf_REPLY_READ_OUT(i) <= reg_current_reply_reading_TRM(i) --current_reply_reading_TRM(i)
or reg_current_reply_reading_HDR(i) --current_reply_reading_HDR(i)
- or (reg_current_reply_auto_reading_DHDR(i) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1))
--- or current_reply_auto_reading_DHDR(i) --current_reply_auto_reading_DHDR(i)
+ or reg_current_reply_auto_reading_DHDR(i)
or saved_reading_padding(i)
or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2));
-- or (reply_fsm_state(4) and reply_reading_H0(i));
current_reply_reading_DHDR(i) <= '1' when current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_DAT
and last_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_HDR else '0';
current_reply_reading_TRM(i) <= '1' when current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_TRM else '0';
- current_reply_auto_reading_DHDR(i) <= '1' when current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0'
- else '0';
- PROC_reading_signals : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i);
- reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i);
- reg_current_reply_reading_DHDR(i) <= current_reply_reading_DHDR(i);
- reg_current_reply_auto_reading_DHDR(i) <= current_reply_auto_reading_DHDR(i);
- end if;
- end process;
+
+ PROC_reading_signals : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i);
+ reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i);
+ reg_current_reply_reading_DHDR(i) <= current_reply_reading_DHDR(i);
+ if (current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH) = "00")
+ or current_reply_reading_HDR(i) = '1' then
+ reg_current_reply_auto_reading_DHDR(i) <= '1';
+ else
+ reg_current_reply_auto_reading_DHDR(i) <= '0';
+ end if;
+ end if;
+ end process;
end generate;
end generate;
gen_reply_mux2 : for i in 0 to c_NUM_WIDTH-1 generate
- packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading,packet_counter)
+ packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading)
variable tmp_pm : std_logic;
begin
tmp_pm := '0';
--REPLY POOL state machine
----------------------------------
- reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, reply_reading_F1,
+ reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter,
send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2, got_all_DHDR,
comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, not_reading_HDR,
- comb_REPLY_muxed_PACKET_NUM, waiting_for_DHDR_word, got_all_reply_starts,
- current_waiting_for_reply, current_REPLY_reading_hdr, locking_point,
- real_activepoints, locked, MY_ADDRESS_IN, reply_adder_ready, reply_adder_result,
- reply_combined_trm_F3, reply_compare_finished, reply_adder_ready,
- reply_adder_overflow, current_reply_reading_DHDR, reply_adder_final_result,
+ waiting_for_DHDR_word, got_all_reply_starts,
+ current_waiting_for_reply, locking_point, last_reply_adder_ready,
+ real_activepoints, locked, MY_ADDRESS_IN, reply_adder_result,
+ reply_combined_trm_F3, reply_compare_finished, reg_current_reply_reading_hdr,
+ reply_adder_final_result, reg_current_reply_reading_dhdr,
evt_seqnr, evt_dtype, evt_random_code, evt_number, number_of_replies,
- current_muxed_reading_DAT,reply_data_counter, current_point_length,
- reply_arbiter_result, REPLY_DATAREADY_IN)
+ reply_data_counter, current_point_length,
+ reply_arbiter_result, reply_reading_f2,current_reply_reading_trm)
begin
release_locked <= '0';
next_state <= current_state;
comb_REPLY_POOL_PACKET_NUM <= packet_counter;
comb_REPLY_POOL_DATA <= (others => '0');
next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints
- and not (reg_current_reply_reading_DHDR and reply_reading_F1);
+ and not (reg_current_reply_reading_DHDR and reply_reading_F2);
last_dhdr_addr <= "000";
next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints;
next_reply_adder_start <= '0';
INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reading_trmF0, reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reading_trmF2, reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal REPLY_combined_trm_F0, REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal REPLY_combined_trm_F2, REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal REPLY_MUX_real_reading : std_logic;
signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal next_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal last_header_addr : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_header_data : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0);
- signal reading_last_hdr,next_reading_last_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
-
--general signals
signal locked, next_locked : std_logic;
signal get_locked, release_locked : std_logic;
signal get_init_locked, release_init_locked: std_logic;
signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal reply_arbiter_result,last_reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0);
type state_type is (SENDING_DATA, SENDING_REPLY_TRM);
signal current_state, next_state : state_type;
signal reply_fsm_state : std_logic;
signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic;
- signal read_from_point_before : std_logic_vector(POINT_NUMBER-1 downto 0);
- signal next_resending_header, resending_header : std_logic;
- signal idle_counter : std_logic_vector(4 downto 0);
- signal idle_time_exceeded : std_logic;
signal reset_i : std_logic;
attribute syn_keep : boolean;
attribute syn_keep of reset_i : signal is true;
signal register_buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0');
begin
-REPLY_HEADER_OUT <= (others => '0');
-
-STAT(0) <= got_trm(0);
-STAT(1) <= got_trm(1);
-STAT(2) <= REPLY_POOL_DATAREADY;
-STAT(3) <= reply_dataready_in_i(0);
-STAT(4) <= buf_REPLY_READ_OUT(0);
-STAT(5) <= comb_REPLY_muxed_DATA(14);
-
-STAT(6) <= reply_data_in_i(14);
-STAT(7) <= reply_data_in_i(30);
-STAT(8) <= '0';--reply_data_in_i(46);
-STAT(9) <= locked;
-
-STAT(15 downto 10) <= (others => '0');
---STAT(15 downto 8) <= data_counter;
-STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm;
-STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0');
-STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
+
+----------------------------------
+--Reset Signals
+----------------------------------
SYNC_RESET : process(CLK)
begin
end if;
end process;
+
+----------------------------------
+--Register Input from IOBufs
+----------------------------------
+
register_buf_REPLY_READ_OUT <= not reply_dataready_in_i or buf_REPLY_READ_OUT;
gen_reply_sync : for i in 0 to POINT_NUMBER-1 generate
end process;
end generate;
+----------------------------------
+--SBuf for init output
+----------------------------------
INIT_POOL_SBUF: trb_net16_sbuf
generic map (
end if;
end process;
-
---choosing reply point
+----------------------------------
+--choosing init point
+----------------------------------
INIT_ARBITER: trb_net_priority_arbiter
generic map (WIDTH => POINT_NUMBER)
port map (
init_arbiter_CLK_EN <= not locked;
init_arbiter_ENABLE <= not init_locked;
---Datapool for Init-Channel
+----------------------------------
+--Merging Data from Init-Channel
+----------------------------------
INIT_muxed_DATAREADY <= or_all(INIT_DATAREADY_IN and buf_INIT_READ_OUT) and not init_locked and INIT_muxed_READ;
INIT_POOL_READ <= and_all(INIT_READ_IN or init_has_read_from_pool or locking_point or not real_activepoints);
INIT_READ_OUT <= buf_INIT_READ_OUT;
end process;
end generate;
-
---init_has_read signal
+----------------------------------
+--Which ports have read data from pool
+----------------------------------
gen_hasread: for i in 0 to POINT_NUMBER-1 generate
process(CLK)
begin
end generate;
-
---signals to obufs
+----------------------------------
+--Output init data to obufs
+----------------------------------
gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate
INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and real_activepoints(i) and not locking_point(i);
INIT_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= INIT_POOL_DATA;
end generate;
+----------------------------------
+--Locking of channels
+----------------------------------
--locked signals
--locked: transfer is running
--init_locked: waiting for reply channel to finish
end if;
end process;
+----------------------------------
+--Connect to init OBufs
+----------------------------------
gen_reply_data_out: for i in 0 to POINT_NUMBER-1 generate
REPLY_DATAREADY_OUT(i) <= REPLY_POOL_DATAREADY and locking_point(i);
REPLY_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= REPLY_POOL_DATA;
REPLY_MUX_real_reading <= REPLY_POOL_next_read; --or_all(REPLY_MUX_reading) and
--REPLY_MUX_reading always contains a 1 (?)
+----------------------------------
--saving necessary data
----------------------------------
save_INIT_TYPE : process(CLK)
end if;
end process;
---REPLY reading and saving HDR
----------------------------------
- gen_reading_hdr : for i in 0 to POINT_NUMBER-1 generate
- process(REPLY_reading_hdr, reply_packet_num_in_i, reply_data_in_i)
- begin
- next_REPLY_reading_hdr(i) <= REPLY_reading_hdr(i);
- if reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then
- next_REPLY_reading_hdr(i) <= '0';
- elsif reply_data_in_i(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_HDR
- and reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
- next_REPLY_reading_hdr(i) <= '1';
- end if;
- end process;
- end generate;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if reset_i = '1' then
- REPLY_reading_hdr <= (others => '0');
- else
- REPLY_reading_hdr <= next_REPLY_reading_hdr;
- end if;
- end if;
- end process;
- current_REPLY_reading_hdr <= next_REPLY_reading_hdr or REPLY_reading_hdr;
-
- gen_saving_hdr : for i in 0 to POINT_NUMBER-1 generate
- last_HDR_RAM : ram_dp
- generic map(
- depth => 3,
- width => 16
- )
- port map(
- CLK => CLK,
- wr1 => current_REPLY_reading_hdr(i),
- a1 => reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- din1 => reply_data_in_i((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- dout1 => open,
- a2 => last_header_addr,
- dout2 => last_header_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
- );
- end generate;
- last_header_addr <= packet_counter;
-
-
-
--REPLY reading and merging TRM
----------------------------------
gen_reading_trm : for i in 0 to POINT_NUMBER-1 generate
gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate
process(CLK)
- variable tmpF1, tmpF2, tmpF3, tmpF0 : std_logic;
+ variable tmpF1, tmpF2, tmpF3 : std_logic;
begin
if rising_edge(CLK) then
if reset_i = '1' or locked = '0' then
- REPLY_combined_trm_F0(j) <= '0';
REPLY_combined_trm_F1(j) <= '0';
REPLY_combined_trm_F2(j) <= '0';
REPLY_combined_trm_F3(j) <= '0';
else
- tmpF0 := '0';
tmpF1 := '0';
tmpF2 := '0';
tmpF3 := '0';
for i in 0 to POINT_NUMBER-1 loop
- tmpF0 := tmpF0 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF0(i));
tmpF1 := tmpF1 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF1(i));
tmpF2 := tmpF2 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF2(i));
tmpF3 := tmpF3 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF3(i));
end loop;
- REPLY_combined_trm_F0(j) <= REPLY_combined_trm_F0(j) or tmpF0;
REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1;
REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2;
REPLY_combined_trm_F3(j) <= REPLY_combined_trm_F3(j) or tmpF3;
end process;
end generate;
-
---real_activepoints can be set between transfers only, but can be cleared at any time
----------------------------------
+--Check which of the available ports are active
+----------------------------------
+--real_activepoints can be set between transfers only, but can be cleared at any time
gen_real_activepoints : process (CLK)
begin
if rising_edge(CLK) then
end if;
end process;
-
+----------------------------------
--count received TRM
----------------------------------
gen_got_trm : process(CLK)
end if;
end process;
---save if data was read from one port
-----------------------------------
- read_before_proc : process(CLK)
- begin
- if rising_edge(CLK) then
- if reset_i = '1' or send_reply_trm = '1' or locked = '0' then
- read_from_point_before <= (others => '0');
- else
- read_from_point_before <= (reply_dataready_in_i and buf_REPLY_READ_OUT) or read_from_point_before;
- end if;
- end if;
- end process;
-
+----------------------------------
--REPLY Counters
----------------------------------
--counter for 16bit words
end if;
end process;
- --counter for idle time
- gen_idle_count : process(CLK)
- begin
- if rising_edge(CLK) then
- if reset_i = '1' or packet_counter = c_H0 then
- idle_counter <= (others => '0');
- idle_time_exceeded <= '0';
- elsif or_all(REPLY_MUX_reading and reply_dataready_in_i) = '0' and idle_time_exceeded = '0' then
- idle_counter <= idle_counter + 1;
- if idle_counter = c_MAX_IDLE_TIME_PER_PACKET then
- idle_time_exceeded <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
+----------------------------------
--REPLY mux select input
----------------------------------
REPLY_ARBITER: trb_net_priority_arbiter
-- we have to care to read multiples of four packets from every point
-- release is currently done after first packet of TRM
- -- when switching from one point to another some data was already read from, we have
- -- to set reading_last_hdr instead of reading_from_point
gen_reply_point_lock : process(reply_point_lock, comb_REPLY_muxed_PACKET_NUM,
reply_arbiter_result, reply_dataready_in_i, comb_REPLY_muxed_DATA,
- REPLY_MUX_reading, last_reply_arbiter_result, got_trm,
- read_from_point_before, resending_header, comb_REPLY_muxed_DATAREADY)
+ REPLY_MUX_reading)
begin
next_point_lock <= reply_point_lock;
REPLY_MUX_reading <= reply_arbiter_result;
--- next_reading_last_hdr <= (others => '0');
--- next_resending_header <= '0';
--release lock if TRM is read
if comb_REPLY_muxed_PACKET_NUM = c_H0 and or_all(REPLY_MUX_reading and reply_dataready_in_i) = '1' then
if comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM then
next_point_lock <= '1';
end if;
end if;
-
--- --release lock when input timed out after even number of data packets (even: because of 32bit alignment)
---
---
--- --trigger resending of header upon switch of arbiter when necessary
--- if or_all(not last_reply_arbiter_result and reply_arbiter_result and not got_trm and read_from_point_before) = '1'
--- or resending_header = '1' then
--- next_resending_header <= '1';
--- next_reading_last_hdr <= reply_arbiter_result;
--- REPLY_MUX_reading <= (others => '0');
--- if resending_header = '1' and comb_REPLY_muxed_PACKET_NUM = c_F3 and comb_REPLY_muxed_DATAREADY = '1' then
--- next_resending_header <= '0';
--- next_reading_last_hdr <= (others => '0');
--- end if;
--- end if;
end process;
---if last_point_lock = 0 and read_from_point_before = 1 and REPLY_MUX_reading \= last_REPLY_MUX_reading then resend_header
gen_point_lock : process(CLK)
begin
reply_point_lock <= '0';
else
reply_point_lock <=next_point_lock;
- last_reply_arbiter_result <= reply_arbiter_result;
--- resending_header <= next_resending_header;
--- reading_last_hdr <= next_reading_last_hdr;
+-- last_reply_arbiter_result <= reply_arbiter_result;
end if;
end if;
end process;
reply_arbiter_CLK_EN <= not next_point_lock;
- resending_header <= '0';
- reading_last_hdr <= (others => '0');
-
+----------------------------------
--REPLY mux
----------------------------------
gen_reply_mux1 : for i in 0 to c_DATA_WIDTH-1 generate
- data_mux : process(reply_data_in_i, REPLY_MUX_reading,last_header_data, reading_last_hdr)
+ data_mux : process(reply_data_in_i, REPLY_MUX_reading)
variable tmp_data : std_logic;
begin
tmp_data := '0';
gen_data_mux : for j in 0 to POINT_NUMBER-1 loop
- tmp_data := tmp_data or (reply_data_in_i(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j))
- or (last_header_data(j*c_DATA_WIDTH+i) and reading_last_hdr(j));
+ tmp_data := tmp_data or (reply_data_in_i(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j));
end loop;
comb_REPLY_muxed_DATA(i) <= tmp_data;
end process;
end generate;
gen_reply_mux2 : for i in 0 to c_NUM_WIDTH-1 generate
- packet_num_mux : process(reply_packet_num_in_i, REPLY_MUX_reading,packet_counter, reading_last_hdr)
+ packet_num_mux : process(reply_packet_num_in_i, REPLY_MUX_reading)
variable tmp_pm : std_logic;
begin
tmp_pm := '0';
gen_pm_mux : for j in 0 to POINT_NUMBER-1 loop
- tmp_pm := tmp_pm or (reply_packet_num_in_i(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j))
- or (packet_counter(i) and reading_last_hdr(j));
+ tmp_pm := tmp_pm or (reply_packet_num_in_i(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j));
end loop;
comb_REPLY_muxed_PACKET_NUM(i) <= tmp_pm;
end process;
end generate;
- comb_REPLY_muxed_DATAREADY <= (or_all(REPLY_MUX_reading and reply_dataready_in_i and not current_REPLY_reading_trm) or or_all(reading_last_hdr)) and REPLY_MUX_real_reading;
+ comb_REPLY_muxed_DATAREADY <= (or_all(REPLY_MUX_reading and reply_dataready_in_i and not current_REPLY_reading_trm)) and REPLY_MUX_real_reading;
+----------------------------------
--REPLY POOL state machine
----------------------------------
- reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, REPLY_combined_trm_F0,
- send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2,
+ reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter,
+ send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2,
comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked,
comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish, REPLY_combined_trm_F3)
begin
end if;
case packet_counter is
when c_F0 =>
- comb_REPLY_POOL_DATA <= x"0000"; --REPLY_combined_trm_F0;
+ comb_REPLY_POOL_DATA <= x"0000";
when c_F1 =>
comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1;
when c_F2 =>
reply_fsm_state <= '1' when current_state= SENDING_REPLY_TRM else '0';
---REPLY sbuf
-----------------------------------
process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
- REPLY_POOL_SBUF: trb_net16_sbuf
+
+----------------------------------
+--REPLY sbuf
+----------------------------------
+ THE_REPLY_POOL_SBUF: trb_net16_sbuf
generic map (
Version => std_SBUF_VERSION
)
SYN_READ_IN => REPLY_POOL_READ
);
+----------------------------------
+--Debugging
+----------------------------------
+ STAT(0) <= got_trm(0);
+ STAT(1) <= got_trm(1);
+ STAT(2) <= REPLY_POOL_DATAREADY;
+ STAT(3) <= reply_dataready_in_i(0);
+ STAT(4) <= buf_REPLY_READ_OUT(0);
+ STAT(5) <= comb_REPLY_muxed_DATA(14);
+
+ STAT(6) <= reply_data_in_i(14);
+ STAT(7) <= reply_data_in_i(30);
+ STAT(8) <= '0';--reply_data_in_i(46);
+ STAT(9) <= locked;
+
+ STAT(15 downto 10) <= (others => '0');
+ --STAT(15 downto 8) <= data_counter;
+ STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm;
+ STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0');
+ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
+
+
end architecture;
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
+ attribute syn_sharing : string;
+
attribute syn_preserve of fifo_data_in : signal is true;
attribute syn_preserve of fifo_packet_num_in : signal is true;
attribute syn_keep of fifo_data_in : signal is true;
attribute syn_keep of fifo_packet_num_in : signal is true;
- attribute syn_sharing : string;
attribute syn_sharing of trb_net16_ibuf_arch : architecture is "off";
+ attribute syn_keep of reg_med_data_in : signal is true;
+ attribute syn_keep of reg_med_dataready_in : signal is true;
+ attribute syn_keep of reg_med_packet_num_in : signal is true;
+
begin
counter_match <= '1';
IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
-
STAT_DEBUG : out std_logic_vector(31 downto 0)
);
end entity;
else
buf_API_READ_OUT <= '1';
first_ipu_read <= '0';
+ --make_compare <= '0';
case state is
when START =>
buf_API_SEND_OUT <= '0';
update_buffers <= '0';
buf_API_SEND_OUT <= '1';
buf_API_DATAREADY_OUT <= '1';
+ --make_compare <= '1';
if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then
dhdr_counter <= dhdr_counter + 1;
case dhdr_counter is
+ component trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port( read_clock_in : in std_logic;
+ write_clock_in : in std_logic;
+ read_enable_in : in std_logic;
+ write_enable_in : in std_logic;
+ fifo_gsr_in : in std_logic;
+ write_data_in : in std_logic_vector(17 downto 0);
+ read_data_out : out std_logic_vector(17 downto 0);
+ full_out : out std_logic;
+ empty_out : out std_logic;
+ fifostatus_out : out std_logic_vector(3 downto 0);
+ valid_read_out : out std_logic;
+ almost_empty_out : out std_logic;
+ almost_full_out : out std_logic
+ );
+ end component;
+ component trb_net16_lsm_sfp is
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available
+ -- status signals
+ SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)
+ SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)
+ SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)
+ SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)
+ SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)
+ SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)
+ -- control signals
+ FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset
+ LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset
+ TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation
+ RX_ALLOW_OUT : out std_logic; -- allow normal receive operation
+ SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)
+ -- debug signals
+ STAT_OP : out std_logic_vector(15 downto 0);
+ CTRL_OP : in std_logic_vector(15 downto 0);
+ STAT_DEBUG : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+
+
+
component trb_net16_med_8_SDR_OS is
component trb_net16_med_ecp_fot_4 is
+ generic(
+ REVERSE_ORDER : integer range 0 to 1 := c_NO
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
+ );
port(
CLK : in std_logic;
CLK_25 : in std_logic;
jspc29 / trbnet.git / commitdiff