config.BaselineAverage <= to_unsigned(8, 4);
config.PolarityInvert <= '1';
- config.check_word1 <= (others => '0');
- config.check_word2 <= (others => '0');
- config.check_word_enable <= '0';
+ config.CheckWord1 <= (others => '0');
+ config.CheckWord2 <= (others => '0');
+ config.CheckWordEnable <= '0';
readout_rx.valid_notiming_trg <= '0';
readout_rx.invalid_trg <= '0';
CFDMultDly : unsigned(3 downto 0);
IntegrateWindow : unsigned(7 downto 0);
TriggerDelay : unsigned(11 downto 0);
- check_word1 : std_logic_vector(RESOLUTION-1 downto 0);
- check_word2 : std_logic_vector(RESOLUTION-1 downto 0);
- check_word_enable : std_logic;
+ CheckWord1 : std_logic_vector(RESOLUTION-1 downto 0);
+ CheckWord2 : std_logic_vector(RESOLUTION-1 downto 0);
+ CheckWordEnable : std_logic;
end record;
end package;
process
begin
wait until rising_edge(CLK);
- if ADC_DATA /= CONF.check_word1 and ADC_DATA /= CONF.check_word2 and CONF.check_word_enable = '1' then
+ if ADC_DATA /= CONF.CheckWord1 and ADC_DATA /= CONF.CheckWord2 and CONF.CheckWordEnable = '1' then
invalid_word_count <= invalid_word_count + 1;
end if;
end process;
baseline <= baseline_average(avg + RESOLUTION - 1 downto avg);
end process proc_baseline_average;
+
+
end architecture arch;