small changes to improve speed (trb_net_old_to_new max frec = 235 MHz).

T. Perez.

diff --git a/trb_net_old_to_new.vhd b/trb_net_old_to_new.vhd
index d8d453d8f007c9cec6618fd74b357182f34cf41d..f59a7bad13dfc374d60dc776cc92e25d39a7eabc 100644 (file)
--- a/trb_net_old_to_new.vhd
+++ b/trb_net_old_to_new.vhd
@@ -82,7 +82,6 @@ entity trb_net_old_to_new is
     );
 end trb_net_old_to_new;
 
---architecture trb_net_old_to_new_arch of trb_net_old_to_new is
 architecture behavioral of trb_net_old_to_new is
 
   -- reconstruct the LVL1 or LVL2 trigger
@@ -105,7 +104,6 @@ architecture behavioral of trb_net_old_to_new is
       ERR              : out std_logic;
       RES              : in  std_logic;
       CLK              : in  std_logic;
--- CLK_10 : in std_logic;
       DVAL             : out std_logic;
       TRIGTAG          : out std_logic_vector(7 downto 0);
       TRIGCODE         : out std_logic_vector(3 downto 0);
@@ -121,11 +119,11 @@ architecture behavioral of trb_net_old_to_new is
 
   type State_Type is (idle, check_code, compare, send, error_1);
   signal present_state, next_state : State_Type;
-  signal do_send_cnt               : unsigned(3 downto 0);
+  signal do_send_cnt               : unsigned(2 downto 0);
 
 
 begin
-  APL_DATA_OUT(7 downto 0)  <= TRIGTAG_ii;
+  APL_DATA_OUT(7 downto 0)  <= TRIGTAG_ii;              
   -----------------------------------------------------------------------------
   -- FIX NON USED OUTPUTS
   -----------------------------------------------------------------------------
@@ -202,7 +200,7 @@ begin
   -- type   : combinational
   -- inputs : present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN
   -- outputs: next_state
-  FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN, TRIGCODE_i, do_send_cnt)
+  FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, TRIGCODE_i, do_send_cnt)
   begin  -- process FSM
     next_state       <= present_state;
     case present_state is
@@ -273,7 +271,7 @@ begin
     end if;
   end process decode_output;
 
-  send_counter : process (CLK, RESET, next_state)
+  send_counter : process (CLK, RESET, present_state)
   begin  -- process send
     if RESET = '1' or present_state = idle then  -- asynchronous reset (active low)
       do_send_cnt <= (others => '0');