fixes

diff --git a/gbe/config.vhd b/gbe/config.vhd
index b62af492632154deea313e87467b6f52d320d45c..4d759e58148b198a4a3a6396ff13349bfba923f6 100644 (file)
--- a/gbe/config.vhd
+++ b/gbe/config.vhd
@@ -12,6 +12,9 @@ package config is
   constant FPGA_TYPE              : integer  := 5;  --3: ECP3, 5: ECP5
 
   constant FPGA_SIZE              : string   := "85KUM";
+
+-- Link speed
+  constant LINK_SPEED             : integer  := 125; -- 125: 1.25Gbps, 200: 2.00Gbps
   
 -- select channel 0 or 1 in DCU
   constant SERDES_NUM             : integer  := 0;

diff --git a/gbe/config_compile_gsi.pl b/gbe/config_compile_gsi.pl
index 592877b6edbef2c28148dc88b835fcc63390aca4..316e2e7ebb32b1683e648c24919085c441544bdb 100644 (file)
--- a/gbe/config_compile_gsi.pl
+++ b/gbe/config_compile_gsi.pl
@@ -15,7 +15,7 @@ pinout_file                  => 'tomcat_prototype',
 par_options                  => '../par.p2t',
     
 include_TDC                  => 0,
-include_GBE                  => 0,
+include_GBE                  => 1,
 
 firefox_open                 => 0,
 twr_number_of_errors         => 20,

diff --git a/gbe/tomcat_gbe.prj b/gbe/tomcat_gbe.prj
index 9c6dbd22fbc73d5bb752647b4ac14de81d0fdbd3..ed6c19928267e0a98bcbaa56a0efdbff4b1d6109 100644 (file)
--- a/gbe/tomcat_gbe.prj
+++ b/gbe/tomcat_gbe.prj
@@ -59,77 +59,18 @@ add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-#add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
 
 #Basic Infrastructure
 add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
 add_file -vhdl -lib work "../../TOMcat/code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-
-#I2C stuff
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire2.vhd"
-
-#GbE
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
-add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
-
-add_file -vhdl -lib work "../../TOMcat/cores/serdes_gbe.vhd"
-add_file -verilog -lib work "../../TOMcat/cores/pcs_gbe_softlogic.v"
-add_file -verilog -lib work "../../TOMcat/cores/sgmii_core_bb.v"
-
-# tsmac
-# serdes_gbe
-
-
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+#add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
 
 #Fifos
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
@@ -158,9 +99,6 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16
 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
 
 
-####################################################################################################
-
-
 #Flash & Reload, Tools
 add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
@@ -168,7 +106,6 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../TOMcat/code/tomcat_tools.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
@@ -189,16 +126,14 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 
 #Media interface
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
-
-
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
 
 #########################################
 #add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_inv/serdes_sync_0.vhd"
@@ -266,36 +201,92 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
 
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire2.vhd"
 
-#add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
-#add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-#add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-#add_file -vhdl -lib work "tdc_release/Channel.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
-#add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
-#add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
-#add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
-#add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-#add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
-#add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
-#add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
-#add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
-#add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-#add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
-#add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+add_file -vhdl -lib work "../../TOMcat/cores/serdes_gbe.vhd"
+add_file -verilog -lib work "../../TOMcat/cores/serdes_gbe_softlogic.v"
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+
+
 add_file -vhdl -lib work "./tomcat_gbe.vhd"

diff --git a/gbe/tomcat_gbe.vhd b/gbe/tomcat_gbe.vhd
index ec948cabe3e2729bc627486984cfdfc31f0a506b..9892f68b1c9758ffc1ccef10c9a2eb2af8f397ea 100644 (file)
--- a/gbe/tomcat_gbe.vhd
+++ b/gbe/tomcat_gbe.vhd
@@ -141,6 +141,8 @@ architecture arch of tomcat_gbe is
   
 begin
 
+  PROGRAMN <= '1';
+
 -------------------------------------------------------------------------------
 -- Clock & Reset Handling
 -------------------------------------------------------------------------------

diff --git a/prototype/par.p2t b/prototype/par.p2t
index cfeb9c515cfa03cd529c9974a4980a9a96cd4d1a..164972dc347adde44e0af459d591a9199591928c 100644 (file)
--- a/prototype/par.p2t
+++ b/prototype/par.p2t
@@ -1,7 +1,7 @@
 -w
 -l 5
 -s 10
--t 13 # seed setting here!
+-t 11 # seed setting here! # was 13
 -c 2
 -e 2
 -i 10

diff --git a/prototype/tomcat_template.vhd b/prototype/tomcat_template.vhd
index 57718a6f85c5bf686e48c2ca6e08fe7ac33735d8..a22493da535cb06ea9556e392d6be6a63e46ad6f 100644 (file)
--- a/prototype/tomcat_template.vhd
+++ b/prototype/tomcat_template.vhd
@@ -101,6 +101,7 @@ architecture arch of tomcat_template is
   signal master_clk_i                : std_logic;
   signal tx_pll_lol_dual_a           : std_logic;
   signal tx_clk_avail_i              : std_logic;
+
   signal word_sync_i                 : std_logic;
   signal tx_pcs_rst_i                : std_logic;
   signal link_tx_ready_i             : std_logic;
@@ -222,12 +223,10 @@ begin
 
 -------------------------------------------------------------------------------
 -------------------------------------------------------------------------------
-trigger_in_i       <= INTCOM(0); -- BUG: we need a "timing trigger" 
+trigger_in_i       <= TIMING_TEST; -- BUG: we need a "timing trigger" 
 -- at least 100ns!
 
-INTCOM(9 downto 1) <= (others => '0');
-
-TIMING_TEST        <= rx_dlm;
+INTCOM(19 downto 0) <= (others => '0');
         
 -------------------------------------------------------------------------------
 -- Endpoint
@@ -329,7 +328,8 @@ TIMING_TEST        <= rx_dlm;
       DEBUG_OUT          => debug_tools
     );
 
-  led_off        <= additional_reg(0);  
+  led_off        <= additional_reg(0);  --TIMING_TEST        <= rx_dlm;
+
 
   -- FlashROM external connections
   FLASH_OVERRIDE <= not additional_reg(1);