DEFINE PORT GROUP "fpga_aux_from_board1_group" "fpga_aux_from_board1*";
IOBUF GROUP "fpga_aux_from_board1_group" IO_TYPE=LVCMOS25;
-LOCATE COMP "testpulse2_to_board1" SITE "K23";
-LOCATE COMP "testpulse1_to_board1" SITE "K22";
+LOCATE COMP "testpulse1_to_board1" SITE "K23";
+LOCATE COMP "testpulse2_to_board1" SITE "K22";
IOBUF PORT "testpulse2_to_board1" IO_TYPE=LVCMOS25 ;
IOBUF PORT "testpulse1_to_board1" IO_TYPE=LVCMOS25 ;
LOCATE COMP "pulldown_to_mupix1" SITE "D3";
IOBUF PORT "pulldown_to_mupix1" IO_TYPE=LVCMOS25 ;
LOCATE COMP "priout_from_mupix1" SITE "L6";
-IOBUF PORT "priout_from_mupix1" IO_TYPE=LVCMOS25 ;
\ No newline at end of file
+IOBUF PORT "priout_from_mupix1" IO_TYPE=LVCMOS25 ;
+
+############################################################
+#unused pins on connector
+############################################################
+LOCATE COMP "not_connected_0" SITE "AD1";
+LOCATE COMP "not_connected_1" SITE "AD2";
+LOCATE COMP "not_connected_2" SITE "AB3";
+LOCATE COMP "not_connected_3" SITE "AB4";
+LOCATE COMP "not_connected_4" SITE "W9";
+LOCATE COMP "not_connected_5" SITE "F1";
+LOCATE COMP "not_connected_6" SITE "P1";
+LOCATE COMP "not_connected_7" SITE "P2";
+LOCATE COMP "not_connected_8" SITE "R1";
+LOCATE COMP "not_connected_9" SITE "M6";
+LOCATE COMP "not_connected_10" SITE "D2";
+LOCATE COMP "not_connected_11" SITE "D1";
+LOCATE COMP "not_connected_12" SITE "C1";
+
+LOCATE COMP "not_connected_13" SITE "J23";
+LOCATE COMP "not_connected_14" SITE "H23";
+LOCATE COMP "not_connected_15" SITE "F24";
+LOCATE COMP "not_connected_16" SITE "G24";
+#not_connected_17 is input only
+LOCATE COMP "not_connected_18" SITE "AB26";
+LOCATE COMP "not_connected_19" SITE "H24";
+LOCATE COMP "not_connected_20" SITE "G25";
+LOCATE COMP "not_connected_21" SITE "K24";
+LOCATE COMP "not_connected_22" SITE "U26";
+LOCATE COMP "not_connected_23" SITE "G6";
+LoCATE COMP "not_connected_24" SITE "K8";
+LOCATE COMP "not_connected_25" SITE "J7";
+DEFINE PORT GROUP "not_connected_group" "not_connected*";
+IOBUF GROUP "not_connected_group" IO_TYPE=LVCMOS25;
+
+###########################################################
+##Relax some timing constraints
+###########################################################
+MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
--data from mupix interface
mupixdata_in : in std_logic_vector(31 downto 0);
mupixdatawr_in : in std_logic;
- mupixendofevent_in : in std_logic;
--response from fee (to trb fifo)
fee_data_out : out std_logic_vector(31 downto 0);
signal hitbus_buffer : std_logic;
--ToT Histogram
- type hithisto_fsm_type is (idle, hitbus_high);
+ type hithisto_fsm_type is (idle, hitbus_high, wait_for_postOscillation);
signal hithisto_fsm : hithisto_fsm_type := idle;
signal hitbus_counter : unsigned(HistogramRange - 1 downto 0); --duration of hitbus high
+ signal postOscillationCounter : unsigned(HistogramRange - 1 downto 0);
signal hitbus_HistoWrAddr : std_logic_vector(HistogramRange - 1 downto 0);
signal hitbus_WriteBin : std_logic;
signal hitbus_BinValue : std_logic_vector(15 downto 0);
signal reading_histo_mem : std_logic := '0'; --read in progress
signal readcounter : unsigned(HistogramRange - 1 downto 0) := (others => '0');
-
-
-
+
begin
Histogram_1 : Histogram
HitBusHisto : process(clk)
begin -- process HitBusHisto
if rising_edge(clk) then
+ hitbus_WriteBin <= '0';
+ postOscillationCounter <= (others => '0');
case hithisto_fsm is
when idle =>
- --hitbus_counter <= (others => '0');
- hitbus_WriteBin <= '0';
+ hitbus_counter <= (others => '0');
if hitbus_i = "01" then --rising edge
- hitbus_counter <= to_unsigned(0, HistogramRange);
hithisto_fsm <= hitbus_high;
end if;
when hitbus_high =>
hitbus_counter <= hitbus_counter + 1;
if hitbus_i = "10" then --falling edge
- hitbus_WriteBin <= '1';
- hitbus_HistoWrAddr <= std_logic_vector(hitbus_counter);
- hithisto_fsm <= idle;
+ hithisto_fsm <= wait_for_postOscillation;
end if;
+ when wait_for_postOscillation =>
+ postOscillationCounter <= postOscillationCounter + 1;
+ if(to_integer(postOscillationCounter) = 5) then --wait 5 clock cycles
+ hitbus_WriteBin <= '1';
+ hitbus_HistoWrAddr <= std_logic_vector(hitbus_counter);
+ hithisto_fsm <= idle;
+ end if;
+ if(hitbus_i = "01") then --new rising edge cut belong to the same event
+ hitbus_counter <= hitbus_counter + postOscillationCounter + 1;
+ hithisto_fsm <= hitbus_high;
+ end if;
end case;
end if;
end process HitBusHisto;
latency_fsm <= waittime;
wait_counter <= wait_counter + 1;
end if;
+
when waittime =>
wait_counter <= wait_counter + 1;
if std_logic_vector(wait_counter) = histo_ctrl(31 downto 16) then
PORT_NUMBER => NUM_PORTS,
PORT_ADDRESSES
- => (0 => x"0020", -- MuPix Interface Control
+ => (0 => x"0500", -- MuPix Interface Control
1 => x"0040", -- Sensorboard DACs
2 => x"0060", -- Injection Control
3 => x"0080", -- MuPix DACs
others => x"0000"),
PORT_ADDR_MASK
- => (0 => 6, -- MuPix Interface Control
+ => (0 => 8, -- MuPix Interface Control
1 => 4, -- Sensorboard DACs
2 => 4, -- Injection Control
3 => 4, -- MuPix DACs
Reset => reset,
MuPixData_in => memdata,
MuPixDataWr_in => memwren,
- MuPixEndOfEvent_in => ro_mupix_busy,
FEE_DATA_OUT => buffer_data,
FEE_DATA_WRITE_OUT => buffer_data_valid,
FEE_DATA_FINISHED_OUT => open,
SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8));
-
+ --set unused signals to board 0
+ fpga_led_to_board <= (others => '0');
+ fpga_aux_to_board(3 downto 1) <= (others => '0');
+
end Behavioral;
type ro_state_type is (waiting, readman, loadpix, pulld, loadcol, readcol, hitgenerator, hitgeneratorwait, pause);
signal state : ro_state_type := waiting;
-
-
+
signal delcounter : unsigned(7 downto 0) := (others => '0');
signal delaycounters1 : std_logic_vector(31 downto 0) := (others => '0');
signal delaycounters2 : std_logic_vector(31 downto 0) := (others => '0');
signal gen_hit_col : std_logic_vector(5 downto 0) := (others => '0');
signal gen_hit_row : std_logic_vector(5 downto 0) := (others => '0');
- signal gen_hit_time : std_logic_vector(7 downto 0) := (others => '0');
-
+
signal testoutro : std_logic_vector (31 downto 0) := (others => '0');
--Control Registers
signal ignorehitflag : std_logic := '0';
+ --readout signal registers
signal priout_reg : std_logic := '0';
+ signal ld_pix_reg : std_logic := '0';
+ signal pulldown_reg : std_logic := '0';
+ signal ld_col_reg : std_logic := '0';
+ signal rd_col_reg : std_logic := '0';
+
begin
-----------------------------------------------------------------------------
--SLV Bus Handler
- --x0020: Readoutregister
- --x0021: Readout Controlbits (manual readout)
- --x0022: Timestamp Controlbits
- --x0023: Hit Generator
- --x0024: Delay Counters 1
- --x0025: EventCounter
- --x0026: Pause Register
- --x0027: Delay Counters 2
- --x0028: Divider for graycounter clock
- --x0029: mask flag for (col,row) = (0,0)
- --x0030: testoutro
- --x0031: Sensor-ID
- --x0032: maximal frame size
+ --x0500: Readoutregister
+ --x0501: Readout Controlbits (manual readout)
+ --x0502: Timestamp Controlbits
+ --x0503: Hit Generator
+ --x0504: Delay Counters 1
+ --x0505: EventCounter
+ --x0506: Pause Register
+ --x0507: Delay Counters 2
+ --x0508: Divider for graycounter clock
+ --x0509: mask flag for (col,row) = (0,0)
+ --x0510: testoutro
+ --x0511: Sensor-ID
+ --x0512: maximal frame size
-----------------------------------------------------------------------------
SLV_HANDLER : process(clk)
if SLV_READ_IN = '1' then
case SLV_ADDR_IN is
- when x"0020" =>
+ when x"0500" =>
SLV_DATA_OUT <= roregister;
SLV_ACK_OUT <= '1';
- when x"0021" =>
+ when x"0501" =>
SLV_DATA_OUT <= rocontrolbits;
SLV_ACK_OUT <= '1';
- when x"0022" =>
+ when x"0502" =>
SLV_DATA_OUT <= timestampcontrolbits;
SLV_ACK_OUT <= '1';
- when x"0023" =>
+ when x"0503" =>
SLV_DATA_OUT <= generatehitswait;
SLV_ACK_OUT <= '1';
- when x"0024" =>
+ when x"0504" =>
SLV_DATA_OUT <= delaycounters1;
SLV_ACK_OUT <= '1';
- when x"0025" =>
+ when x"0505" =>
SLV_DATA_OUT <= std_logic_vector(eventcounter);
SLV_ACK_OUT <= '1';
- when x"0026" =>
+ when x"0506" =>
SLV_DATA_OUT <= pauseregister;
SLV_ACK_OUT <= '1';
- when x"0027" =>
+ when x"0507" =>
SLV_DATA_OUT <= delaycounters2;
SLV_ACK_OUT <= '1';
- when x"0028" =>
+ when x"0508" =>
SLV_DATA_OUT <= graycounter_clkdiv_counter;
SLV_ACK_OUT <= '1';
- when x"0029" =>
+ when x"0509" =>
SLV_DATA_OUT(0) <= ignorehitflag;
SLV_ACK_OUT <= '1';
- when x"0030" =>
+ when x"0510" =>
SLV_DATA_OUT <= testoutro;
SLV_ACK_OUT <= '1';
- when x"0031" =>
+ when x"0511" =>
SLV_DATA_OUT <= sensor_id;
SLV_ACK_OUT <= '1';
- when x"0032" =>
+ when x"0512" =>
SLV_DATA_OUT <= maxNumberHits;
SLV_ACK_OUT <= '1';
+ when x"0513" =>
+ SLV_DATA_OUT(0) <= ro_busy_int;
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
if SLV_WRITE_IN = '1' then
case SLV_ADDR_IN is
- when x"0020" =>
+ when x"0500" =>
roregister <= SLV_DATA_IN;
roregwritten <= '1'; --trigger the readout
SLV_ACK_OUT <= '1';
- when x"0021" =>
+ when x"0501" =>
rocontrolbits <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0022" =>
+ when x"0502" =>
timestampcontrolbits <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0023" =>
+ when x"0503" =>
generatehitswait <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0024" =>
+ when x"0504" =>
delaycounters1 <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0026" =>
+ when x"0506" =>
pauseregister <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0027" =>
+ when x"0507" =>
delaycounters2 <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0028" =>
+ when x"0508" =>
graycounter_clkdiv_counter <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0029" =>
+ when x"0509" =>
ignorehitflag <= SLV_DATA_IN(0);
SLV_ACK_OUT <= '1';
- when x"0031" =>
+ when x"0511" =>
sensor_id <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
- when x"0032" =>
+ when x"0512" =>
maxNumberHits <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
when others =>
-----------------------------------------------------------------------------
--MuPix 3/4/6 Readout Statemachine
-----------------------------------------------------------------------------
-
ro_statemachine : process(rst, clk)
begin
if rising_edge(clk) then
if(rst = '1') then
state <= waiting;
- ldpix <= '0';
- ldcol <= '0';
- rdcol <= '0';
- pulldown <= '0';
+ ld_pix_reg <= '0';
+ ld_col_reg <= '0';
+ rd_col_reg <= '0';
+ pulldown_reg <= '0';
memwren <= '0';
ro_busy_int <= '0';
eventcounter <= (others => '0');
else
testoutro <= (others => '0');
testoutro(31) <= priout;
-
+ memwren <= '0';
+ memdata <= (others => '0');
+ endofevent <= '0';
+ ro_busy_int <= '0';
+ ld_pix_reg <= '0';
+ pulldown_reg <= '0';
+ ld_col_reg <= '0';
+ rd_col_reg <= '0';
case state is
when pause =>
pausecounter <= pausecounter +1;
state <= waiting;
pausecounter <= (others => '0');
end if;
- ldpix <= '0';
- ldcol <= '0';
- rdcol <= '0';
- pulldown <= '0';
- memwren <= '0';
- endofevent <= '0';
- ro_busy_int <= '0';
when waiting =>
testoutro(1) <= '1';
- memwren <= '0';
- ro_busy_int <= '0';
- endofevent <= '0';
delcounter <= (others => '0');
hitcounter <= (others => '0');
eventcounter <= eventcounter;
if(reseteventcount = '1') then
eventcounter <= (others => '0');
end if;
- ldpix <= '0';
- ldcol <= '0';
- rdcol <= '0';
- pulldown <= '0';
if(readmanual = '1') then
state <= readman;
elsif(continousread = '1' or readnow = '1' or(triggering = '1' and trigger_ext = '1' and generatetriggeredhits = '0')) then
state <= loadpix;
- ldpix <= '1';
+ ld_pix_reg <= '1';
delcounter <= unsigned(delaycounters1(7 downto 0));
eventcounter <= eventcounter + 1;
elsif(generatetriggeredhits = '1' and trigger_ext = '1') then
when readman =>
testoutro(9) <= '1';
ro_busy_int <= '1';
- ldpix <= rocontrolbits(0);
- pulldown <= rocontrolbits(1);
- ldcol <= rocontrolbits(2);
- rdcol <= rocontrolbits(3);
+ ld_pix_reg <= rocontrolbits(0);
+ pulldown_reg <= rocontrolbits(1);
+ ld_col_reg <= rocontrolbits(2);
+ rd_col_reg <= rocontrolbits(3);
if(readmanual = '1') then
state <= readman;
else
state <= waiting;
end if;
- endofevent <= '0';
when loadpix =>
ro_busy_int <= '1';
testoutro(2) <= '1';
- ldpix <= '0';
- delcounter <= delcounter - 1;
- memwren <= '0';
- state <= loadpix;
- if(delcounter = "00000100") then -- write event header
+ --data output
+ case delcounter is
+ when "00000010" =>
memdata <= sensor_id;
memwren <= '1';
- elsif(delcounter = "0000011") then -- write event header
- memdata <= "11111010101111101010101110111010"; --0xFABEABBA
+ when "00000001" =>
+ memdata <= x"FABEABBA";
memwren <= '1';
- elsif(delcounter = "00000010") then -- write event counter
+ when "00000000" =>
memdata <= std_logic_vector(eventcounter);
memwren <= '1';
- end if;
+ when others =>
+ memdata <= (others => '0');
+ memwren <= '0';
+ end case;
+ --state machine
if(delcounter = "00000000") then
state <= pulld;
- pulldown <= '1';
+ pulldown_reg <= '1';
delcounter <= unsigned(delaycounters1(15 downto 8));
+ else
+ pulldown_reg <= '0';
+ delcounter <= delcounter - 1;
+ state <= loadpix;
end if;
- endofevent <= '0';
when pulld =>
+ ro_busy_int <= '1';
testoutro(3) <= '1';
- memwren <= '0';
- if unsigned(delaycounters1(15 downto 8)) = delcounter then
- pulldown <= '0';
- end if;
delcounter <= delcounter - 1;
state <= pulld;
if(delcounter = "00000000") then
state <= loadcol;
- ldcol <= '1';
+ ld_col_reg <= '1';
delcounter <= unsigned(delaycounters1(23 downto 16));
end if;
- endofevent <= '0';
when loadcol =>
+ ro_busy_int <= '1';
testoutro(4) <= '1';
- memwren <= '0';
- if(delcounter = unsigned(delaycounters1(23 downto 16))) then
- ldcol <= '0';
- end if;
delcounter <= delcounter - 1;
state <= loadcol;
- endofevent <= '0';
- if(delcounter = "00000000" and priout = '1') then
- state <= readcol;
- rdcol <= '1';
- delcounter <= unsigned(delaycounters1(31 downto 24));
- elsif(delcounter = "00000000") then
- -- end of event
- memwren <= '1';
- memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
- endofevent <= '1';
- state <= pause;
+ if(delcounter = "00000000") then
+ if priout = '1' then
+ state <= readcol;
+ rd_col_reg <= '1';
+ delcounter <= unsigned(delaycounters1(31 downto 24));
+ else
+ memwren <= '1';
+ memdata <= x"BEEFBEEF";
+ endofevent <= '1';
+ state <= pause;
+ end if;
end if;
when readcol =>
+ ro_busy_int <= '1';
testoutro(5) <= '1';
- if(delcounter = unsigned(delaycounters1(31 downto 24)) - unsigned(delaycounters2(15 downto 8))) then
- rdcol <= '0';
- end if;
delcounter <= delcounter - 1;
- memwren <= '0';
state <= readcol;
- endofevent <= '0';
+ --issue read signal
+ if(delcounter > unsigned(delaycounters1(31 downto 24)) - unsigned(delaycounters2(15 downto 8))) then
+ rd_col_reg <= '1';
+ end if;
+ --sample priout
if (std_logic_vector(delcounter) = delaycounters2(23 downto 16)) then
priout_reg <= priout;
end if;
+ --write hit information
if(std_logic_vector(delcounter) = delaycounters2(31 downto 24)) then
- memdata <= "111100001111" & hit_col & hit_row & hit_time; --0xF0F
+ memdata <= x"F0F" & hit_col & hit_row & hit_time;
memwren <= '1';
if(ignorehitflag = '1' and (hit_col = "000000" and hit_row = "000000")) then
memwren <= '0';
end if;
hitcounter <= hitcounter + 1;
state <= readcol;
- elsif(delcounter = "00000000" and hitcounter = unsigned(maxNumberHits(10 downto 0))) then
- -- maximal number of hits reaced
- -- force end of event
- memwren <= '1';
- memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
- endofevent <= '1';
- state <= pause;
- elsif(delcounter = "00000000" and (priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1'))) then
- state <= readcol;
- rdcol <= '1';
- delcounter <= unsigned(delaycounters1(31 downto 24));
elsif(delcounter = "00000000") then
- state <= pulld;
- pulldown <= '1';
- delcounter <= unsigned(delaycounters2(7 downto 0));
+ if(hitcounter = unsigned(maxNumberHits(10 downto 0))) then
+ -- maximal number of hits reaced
+ -- force end of event
+ memwren <= '1';
+ memdata <= x"BEEFBEEF"; --0xBEEFBEEF
+ endofevent <= '1';
+ state <= pause;
+ else
+ if (priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1')) then
+ state <= readcol;
+ rd_col_reg <= '1';
+ delcounter <= unsigned(delaycounters1(31 downto 24));
+ else
+ state <= pulld;
+ pulldown_reg <= '1';
+ delcounter <= unsigned(delaycounters2(7 downto 0));
+ end if;
+ end if;
end if;
when hitgenerator =>
testoutro(6) <= '1';
state <= hitgenerator;
delcounter <= delcounter - 1;
- if(delcounter = "00000100") then -- write event header
+ if(delcounter = "00000011") then -- write event header
state <= hitgenerator;
memdata <= sensor_id;
memwren <= '1';
generatehitswaitcounter <= unsigned(generatehitswait);
gen_hit_col <= (others => '0');
gen_hit_row <= (others => '0');
- gen_hit_time <= (others => '0');
- endofevent <= '0';
- elsif(delcounter = "00000011") then -- write event header
+ elsif(delcounter = "00000010") then -- write event header
state <= hitgenerator;
- memdata <= "11111010101111101010101110111010"; --0xFABEABBA
+ memdata <= x"FABEABBA"; --0xFABEABBA
memwren <= '1';
- endofevent <= '0';
- elsif(delcounter = "00000010") then -- write event counter
+ elsif(delcounter = "00000001") then -- write event counter
state <= hitgenerator;
memdata <= std_logic_vector(eventcounter);
memwren <= '1';
- endofevent <= '0';
- elsif(delcounter = "00000010") then
- state <= hitgenerator;
- memwren <= '0';
- endofevent <= '0';
- elsif(delcounter = "00000001") then -- write trigger number
- state <= hitgenerator;
- memdata <= (others => '0'); --empty trigger number
- memwren <= '1';
- endofevent <= '0';
- elsif(delcounter = "00000000" and ngeneratehitscounter > "0000000000000000") then
- state <= hitgenerator;
- delcounter <= delcounter;
- ngeneratehitscounter <= ngeneratehitscounter - 1;
- gen_hit_col <= std_logic_vector(unsigned(gen_hit_col) + 5);
- gen_hit_row <= std_logic_vector(unsigned(gen_hit_row) + 7);
- if(gen_hit_row > "10000") then
- gen_hit_row <= "000000";
+ elsif(delcounter = "00000000") then
+ if ngeneratehitscounter > "0000000000000000" then
+ state <= hitgenerator;
+ delcounter <= delcounter;
+ ngeneratehitscounter <= ngeneratehitscounter - 1;
+ gen_hit_col <= std_logic_vector(unsigned(gen_hit_col) + 5);
+ gen_hit_row <= std_logic_vector(unsigned(gen_hit_row) + 7);
+ if(gen_hit_row > "10000") then
+ gen_hit_row <= "000000";
+ end if;
+ memdata <= x"F0F" & "0" & gen_hit_col(4 downto 0) & gen_hit_row & graycount;
+ memwren <= '1';
+ else
+ if generatehits = '0' then
+ state <= waiting;
+ -- end of event
+ memwren <= '1';
+ memdata <= x"BEEFBEEF";
+ endofevent <= '1';
+ else
+ state <= hitgeneratorwait;
+ -- end of event
+ memwren <= '1';
+ memdata <= x"BEEFBEEF";
+ endofevent <= '1';
+ end if;
end if;
- memdata <= "111100001111" & "0" & gen_hit_col(4 downto 0) & gen_hit_row & graycount; --0xF0F
- memwren <= '1';
- endofevent <= '0';
- elsif(delcounter = "00000000" and ngeneratehitscounter = "0000000000000000" and generatehits = '0') then
- state <= waiting;
- -- end of event
- memwren <= '1';
- memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
- endofevent <= '1';
- elsif(delcounter = "00000000" and ngeneratehitscounter = "0000000000000000" and generatehits = '1') then
- state <= hitgeneratorwait;
- -- end of event
- memwren <= '1';
- memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
- endofevent <= '1';
else
state <= hitgenerator;
- memwren <= '0';
- endofevent <= '0';
end if;
when hitgeneratorwait =>
- ro_busy_int <= '0';
state <= hitgeneratorwait;
testoutro(7) <= '1';
- memwren <= '0';
- endofevent <= '0';
generatehitswaitcounter <= generatehitswaitcounter - 1;
if(to_integer(generatehitswaitcounter) = 0)then
state <= hitgenerator;
delcounter <= "00000100";
eventcounter <= eventcounter + 1;
end if;
-
when others =>
testoutro(8) <= '1';
state <= waiting;
- endofevent <= '0';
end case;
end if;
end if;
end if;
end process;
- resetgraycounter <= rst or timestampreset_in;
+ resetgraycounter <= timestampreset_in or timestampcontrolbits(9);
grcount : Graycounter
generic map(
port map(
clk => clk,
reset => resetgraycounter,
- sync_reset => timestampcontrolbits(9),
clk_divcounter => graycounter_clkdiv_counter(7 downto 0),
counter => graycount
);
ro_busy <= ro_busy_int;
+ ldpix <= ld_pix_reg;
+ pulldown <= pulldown_reg;
+ ldcol <= ld_col_reg;
+ rdcol <= rd_col_reg;
end RTL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
+
entity TimeWalk is
port (
clk : in std_logic;
signal latencycounter : unsigned(15 downto 0) := (others => '0');
signal hitbuscounter : unsigned(15 downto 0) := (others => '0');
+ signal hitbus_delayed : std_logic := '0';
signal hitbus_edge : std_logic_vector(1 downto 0) := (others => '0');
signal szintillator_trigger_edge : std_logic_vector(1 downto 0) := (others => '0');
- signal hitbusBuffer : std_logic := '0';
- signal szintilatorTriggerBuffer : std_logic := '0';
+ signal szintillator_trigger_buffer : std_logic := '0';
type TimeWalk_fsm_type is (idle, waitforhitbus, measurehitbus, measurement_done);
signal timewalk_fsm : TimeWalk_fsm_type := idle;
+ component SignalDelay is
+ generic (
+ Width : integer;
+ Delay : integer);
+ port (
+ clk_in : in std_logic;
+ write_en_in : in std_logic;
+ delay_in : in std_logic_vector(Delay - 1 downto 0);
+ sig_in : in std_logic_vector(Width - 1 downto 0);
+ sig_out : out std_logic_vector(Width - 1 downto 0));
+ end component SignalDelay;
begin -- architecture TimeWalk_Arch
+ SignalDelay_1: entity work.SignalDelay
+ generic map (
+ Width => 1,
+ Delay => 5)
+ port map (
+ clk_in => clk,
+ write_en_in => '1',
+ delay_in => std_logic_vector(to_unsigned(16, 5)),
+ sig_in(0) => hitbus,
+ sig_out(0) => hitbus_delayed);
+
-- purpose: synchronize signals and edge detection
signal_synchro: process (clk) is
begin -- process clk
if rising_edge(clk) then
- hitbusBuffer <= hitbus;
- szintilatorTriggerBuffer <= szintillator_trigger;
- hitbus_edge <= hitbus_edge(0) & hitbusBuffer;
- szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintilatorTriggerBuffer;
+ hitbus_edge <= hitbus_edge(0) & hitbus_delayed;
+ szintillator_trigger_buffer <= szintillator_trigger;
+ szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer;
end if;
end process signal_synchro;
- TimeWalk_Measurement : process (clk, reset) is
+ TimeWalk_Measurement : process (clk) is
begin -- process TimeWalk_Measurement
if rising_edge(clk) then
measurementFinished <= '0';
measurementData <= (others => '0');
case timewalk_fsm is
when idle =>
- latencycounter <= (others => '0');
- hitbuscounter <= (others => '0');
- if szintillator_trigger_edge = "01" then
- timewalk_fsm <= waitforhitbus;
- latencycounter <= latencycounter + 1;
- end if;
+ latencycounter <= (others => '0');
+ hitbuscounter <= (others => '0');
+ if szintillator_trigger_edge = "01" then
+ timewalk_fsm <= waitforhitbus;
+ end if;
when waitforhitbus =>
- latencycounter <= latencycounter + 1;
- if latencycounter = unsigned(hitbus_timeout(15 downto 0)) then
- timewalk_fsm <= idle;
- elsif hitbus_edge = "01" then
- timewalk_fsm <= measurehitbus;
- hitbuscounter <= hitbuscounter + 1;
- else
- timewalk_fsm <= waitforhitbus;
- end if;
+ latencycounter <= latencycounter + 1;
+ if latencycounter = unsigned(hitbus_timeout(15 downto 0)) then
+ timewalk_fsm <= idle;
+ elsif hitbus_edge = "01" then
+ timewalk_fsm <= measurehitbus;
+ else
+ timewalk_fsm <= waitforhitbus;
+ end if;
when measurehitbus =>
- hitbuscounter <= hitbuscounter + 1;
- timewalk_fsm <= measurehitbus;
- if hitbus_edge = "00" then
- timewalk_fsm <= measurement_done;
- end if;
+ if hitbus_edge = "00" then
+ timewalk_fsm <= measurement_done;
+ else
+ hitbuscounter <= hitbuscounter + 1;
+ timewalk_fsm <= measurehitbus;
+ end if;
when measurement_done =>
- timewalk_fsm <= idle;
- if readyToWrite = '1' then
- measurementData <= std_logic_vector(latencycounter & hitbuscounter);
- measurementFinished <= '1';
- end if;
+ timewalk_fsm <= idle;
+ if readyToWrite = '1' then
+ measurementData <= std_logic_vector(latencycounter & hitbuscounter);
+ measurementFinished <= '1';
+ end if;
when others => null;
end case;
end if;
architecture TimeWalk_arch of TimeWalkWithFiFo is
constant bitsBeforeWriteCounter : integer := 2;
- signal hitbus_timeout : std_logic_vector(31 downto 0) := (others => '0');
-
+ signal hitbus_timeout : std_logic_vector(31 downto 0) := x"00000024";
+
+ signal resetcounters : std_logic := '0';
signal hitbusEdgeCounter : unsigned(31 downto 0) := (others => '0');
signal szintilatorEdgeCounter : unsigned(31 downto 0) := (others => '0');
signal hitbusRisingEdge : std_logic_vector(1 downto 0) := (others => '0');
signal szintilator_trigger_buffer : std_logic := '0';
signal FiFo_Wren : std_logic := '0';
- signal FiFo_Rden : std_logic := '0';
signal FiFo_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal FiFo_data_out : std_logic_vector(31 downto 0) := (others => '0');
signal FiFo_writecounter : std_logic_vector(12 downto 0) := (others => '0');
WrClock => fast_clk,
RdClock => trb_slv_clock,
WrEn => FiFo_Wren,
- RdEn => FiFo_Rden,
+ RdEn => fifo_read_s,
Reset => Reset,
RPReset => Reset,
Q => FiFo_data_out,
szintilator_trigger_buffer <= szintillator_trigger;
hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus_buffer;
szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintilator_trigger_buffer;
- if szintilatorRisingEdge = "01" then
- szintilatorEdgeCounter <= szintilatorEdgeCounter + 1;
- end if;
- if hitbusRisingEdge = "01" then
- hitbusEdgeCounter <= hitbusEdgeCounter + 1;
+ if resetcounters = '1' then
+ szintilatorEdgeCounter <= (others => '0');
+ hitbusEdgeCounter <= (others => '0');
+ else
+ if szintilatorRisingEdge = "01" then
+ szintilatorEdgeCounter <= szintilatorEdgeCounter + 1;
+ end if;
+ if hitbusRisingEdge = "01" then
+ hitbusEdgeCounter <= hitbusEdgeCounter + 1;
+ end if;
end if;
end if;
end process edge_counter;
--0x0403: timeout after szintilator trigger signal
--0x0404: number of rising edges on szintilator
--0x0405: number of rising edges on hitbus
+ --0x0406: reset counters
-----------------------------------------------------------------------------
fifo_status((bitsBeforeWriteCounter - 1) downto 0) <= fifo_empty & FiFo_full;
fifo_status(12 + bitsBeforeWriteCounter downto bitsBeforeWriteCounter) <= FiFo_writecounter;
when x"0403" =>
hitbus_timeout <= slv_data_in;
slv_ack_out <= '1';
+ when x"0406" =>
+ resetcounters <= slv_data_in(0);
+ slv_ack_out <= '1';
when others =>
slv_unknown_addr_out <= '1';
end case;
COUNTWIDTH : integer := 8
);
port (
- clk : in std_logic; -- clock
- reset : in std_logic; -- asynchronous reset
- sync_reset : in std_logic; -- synchronous reset
- clk_divcounter : in std_logic_vector(7 downto 0); -- clockdivider for
- -- graycounter clock
- counter : out std_logic_vector(COUNTWIDTH-1 downto 0) -- counter
+ clk : in std_logic; -- clock
+ reset : in std_logic; -- reset
+ clk_divcounter : in std_logic_vector(7 downto 0); -- clockdivider for
+ -- graycounter clock
+ counter : out std_logic_vector(COUNTWIDTH-1 downto 0) -- counter
);
end Graycounter;
architecture rtl of Graycounter is
- signal msb : std_logic := '0';
+ signal msb : std_logic := '0';
signal counter_reg : std_logic_vector(COUNTWIDTH downto 0) := (others => '0');
signal no_ones_below : std_logic_vector(COUNTWIDTH downto 0) := "000000001";
- signal clk_enable : std_logic := '0';
- signal divcounter : unsigned(7 downto 0) := (others => '0');
+ signal clk_enable : std_logic := '0';
+ signal divcounter : unsigned(7 downto 0) := (others => '0');
begin
msb <= counter_reg(COUNTWIDTH) or counter_reg(COUNTWIDTH-1);
- clock_divider_proc: process (clk) is
+ clock_divider_proc : process (clk) is
begin -- process clock_divider_proc
if rising_edge(clk) then
if reset = '1' then
process(clk, reset)
begin
if (clk'event and clk = '1') then
- if (sync_reset = '1') then
+ if (reset = '1') then
no_ones_below(0) <= '1';
- counter_reg <= (others => '0');
- counter_reg(0) <= '1';
+ counter_reg <= (others => '0');
+ counter_reg(0) <= '1';
else
if clk_enable = '1' then
counter_reg(0) <= not counter_reg(0);
- for i in 1 to COUNTWIDTH-1 loop
- counter_reg(i) <= counter_reg(i) xor (counter_reg(i-1) and no_ones_below(i-1));
- end loop;
- counter_reg(COUNTWIDTH) <= counter_reg(COUNTWIDTH) xor (msb and no_ones_below(COUNTWIDTH-1));
+ for i in 1 to COUNTWIDTH-1 loop
+ counter_reg(i) <= counter_reg(i) xor (counter_reg(i-1) and no_ones_below(i-1));
+ end loop;
+ counter_reg(COUNTWIDTH) <= counter_reg(COUNTWIDTH) xor (msb and no_ones_below(COUNTWIDTH-1));
else
- counter_reg <= counter_reg;
+ counter_reg <= counter_reg;
end if;
end if;
end if;
port (
clk : in std_logic;
reset : in std_logic;
- sync_reset : in std_logic;
clk_divcounter : in std_logic_vector(7 downto 0);
counter : out std_logic_vector(COUNTWIDTH-1 downto 0));
end component;
Reset : in std_logic;
MuPixData_in : in std_logic_vector(31 downto 0);
MuPixDataWr_in : in std_logic;
- MuPixEndOfEvent_in : in std_logic;
FEE_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_WRITE_OUT : out std_logic;
FEE_DATA_FINISHED_OUT : out std_logic;
measurementFinished : out std_logic;
measurementData : out std_logic_vector(31 downto 0));
end component TimeWalk;
+
end mupix_components;
add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd"
add_file -vhdl -lib "work" "sources/TimeWalk.vhd"
-add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
\ No newline at end of file
+add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
+add_file -vhdl -lib "work" "sources/SignalDelay.vhd"
\ No newline at end of file
---------------------------------------------------------------------------
-- END SensorBoard MuPix
---------------------------------------------------------------------------
-
+ not_connected : out std_logic_vector(25 downto 0);
--Flash ROM & Reboot
FLASH_CLK : out std_logic;
begin
+
+ --tie not connected outputs to 0
+ not_connected(25 downto 18) <= (others => '0');
+ not_connected(16 downto 0) <= (others => '0');
---------------------------------------------------------------------------
-- Reset Generation
---------------------------------------------------------------------------
jspc29 / trb3.git / commitdiff