a running pulser

diff --git a/pulser/code/pulser.vhd b/pulser/code/pulser.vhd
index e179e0914fb03bbe9c179f54a8b084e759ff227d..d1116231a6ad044eec921f065ed94f0e795ca99c 100644 (file)
--- a/pulser/code/pulser.vhd
+++ b/pulser/code/pulser.vhd
@@ -82,6 +82,7 @@ signal control_strobes : std_logic_vector(31 downto 0);
 signal pulser_enable   : std_logic_vector(31 downto 0);
 signal pulser_invert   : std_logic_vector(31 downto 0);
 signal pulser_reset    : std_logic;
+signal next_pulser_reset : std_logic;
 
 -- type pulse_ddr_t  is array(0 to 31) of std_logic_vector(3 downto 0);
 -- signal pulse    : pulse_ddr_t;
@@ -106,6 +107,7 @@ multi_ch_pulser_left : for n in 0 to 19 generate
       PULSE_WIDTH => length(n)(23 downto 0),
       OFFSET      => offset(n)(23 downto 0),
       INVERT      => pulser_invert(n),
+      ENABLE      => pulser_enable(n),
       PULSE(0)    => data_left(0)(n),
       PULSE(1)    => data_left(1)(n),
       PULSE(2)    => data_left(2)(n),
@@ -123,6 +125,7 @@ multi_ch_pulser_right : for n in 0 to 9 generate
       PULSE_WIDTH => length(n+20)(23 downto 0),
       OFFSET      => offset(n+20)(23 downto 0),
       INVERT      => pulser_invert(n+20),
+      ENABLE      => pulser_enable(n+20),
       PULSE(0)    => data_right(0)(n),
       PULSE(1)    => data_right(1)(n),
       PULSE(2)    => data_right(2)(n),
@@ -152,8 +155,8 @@ THE_LEFT_DDR : entity work.ddr_20
     reset => '0',
     sclk  => clk_slow_left,
     da0   => data_left(0),
-    da1   => data_left(1),
-    db0   => data_left(2),
+    da1   => data_left(2),
+    db0   => data_left(1),
     db1   => data_left(3),
     q(15 downto 0)  => OUTP(16 downto 1),
     q(19 downto 16) => OUTP_FAN(3 downto 0)
@@ -168,8 +171,8 @@ THE_RIGHT_DDR : entity work.ddr_10
     reset => '0',
     sclk  => clk_slow_right,
     da0   => data_right(0),
-    da1   => data_right(1),
-    db0   => data_right(2),
+    da1   => data_right(2),
+    db0   => data_right(1),
     db1   => data_right(3),
     q     => OUTP_ANA
     );
@@ -185,8 +188,9 @@ THE_RIGHT_DDR : entity work.ddr_10
   proc_ctrlbus : process begin
     wait until rising_edge(SYSCLK);
     BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; BUS_TX.unknown <= '0';
-    control_strobes <= (others => '0');
-    pulser_reset <= RESET;
+    control_strobes   <= (others => '0');
+    next_pulser_reset <= '0';
+    pulser_reset      <= RESET or next_pulser_reset;
     
     if BUS_RX.read = '1' then
       BUS_TX.ack <= '1';
@@ -201,10 +205,10 @@ THE_RIGHT_DDR : entity work.ddr_10
       elsif BUS_RX.addr(7 downto 0) = x"01" then
         BUS_TX.data             <= pulser_invert;
       elsif BUS_RX.addr(7 downto 0) = x"40" then
-        BUS_TX.data(3 downto 0) <= ana1_in_select ;
+        BUS_TX.data(3 downto 0) <= ana1_in_select;
         BUS_TX.data(9 downto 8) <= ana1_out_select;
       elsif BUS_RX.addr(7 downto 0) = x"41" then
-        BUS_TX.data(3 downto 0) <= ana2_in_select ;
+        BUS_TX.data(3 downto 0) <= ana2_in_select;
         BUS_TX.data(9 downto 8) <= ana2_out_select;
       else
         BUS_TX.ack <= '0';
@@ -215,13 +219,13 @@ THE_RIGHT_DDR : entity work.ddr_10
       BUS_TX.ack <= '1';
       if    BUS_RX.addr(7 downto 5) = "100" then
         period(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
-        pulser_reset <= '1';
+        next_pulser_reset <= '1';
       elsif BUS_RX.addr(7 downto 5) = "101" then
         length(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
-        pulser_reset <= '1';
+        next_pulser_reset <= '1';
       elsif BUS_RX.addr(7 downto 5) = "110" then
         offset(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
-        pulser_reset <= '1';
+        next_pulser_reset <= '1';
       elsif BUS_RX.addr(7 downto 0) = x"00" then  
         pulser_enable <= BUS_RX.data;
       elsif BUS_RX.addr(7 downto 0) = x"01" then  

diff --git a/pulser/code/single_channel_pulser.vhd b/pulser/code/single_channel_pulser.vhd
index fce6bde37efb2feeee4e94336bd9aece7e4d97d7..85f565fa4a0845fb6e4fe4bfbe55c4ff886afa84 100644 (file)
--- a/pulser/code/single_channel_pulser.vhd
+++ b/pulser/code/single_channel_pulser.vhd
@@ -17,6 +17,7 @@ entity single_channel_pulser is
       PULSE_WIDTH      : in unsigned(23 downto 0);\r
       OFFSET      : in unsigned(23 downto 0);\r
       INVERT      : in std_logic;\r
+      ENABLE      : in std_logic;\r
       PULSE                            : out std_logic_vector(3 downto 0)\r
     );\r
     \r
@@ -27,8 +28,10 @@ architecture single_channel_pulser_arch of single_channel_pulser is
 signal timer                                                           :       unsigned(23 downto 0) := (others => '0');  \r
 signal last_timer           : unsigned(23 downto 0) := (others => '0');  \r
 signal reset_counter                           :       std_logic;\r
+signal frequency_in         : unsigned(23 downto 0);  \r
 signal frequency_i                                     :       unsigned(23 downto 0);  \r
 signal reset_delay                                     :       std_logic;\r
+signal pulse_width_in       : unsigned(23 downto 0);\r
 signal pulse_width_i                           :       unsigned(23 downto 0);\r
 \r
 type state_type is (idle, generate_pulse, finish);\r
@@ -37,13 +40,21 @@ signal state : state_type;
 \r
 begin\r
 \r
+PROC_REGS : process begin\r
+  wait until rising_edge(CLK);\r
+  if RESET = '1' then\r
+    pulse_width_in <= PULSE_WIDTH;\r
+    frequency_in <= FREQUENCY;\r
+  end if;  \r
+end process;  \r
+\r
        PROC_TIMER : process (CLK)              --it counts \r
                begin\r
                        if rising_edge(CLK) then\r
                                if reset_counter = '1' then     \r
-                                       timer <= (others => '0') after 1 ns; \r
+                                       timer <= (others => '0'); \r
                                else \r
-                                       timer <= timer+1 after 1 ns;\r
+                                       timer <= timer+1;\r
                                end if;\r
                        end if;\r
                end process;\r
@@ -51,8 +62,8 @@ begin
        PROC_FREQUENCY : process (CLK)  --It eliminates the offset of -2 for the frequency  \r
                begin\r
                        if rising_edge(CLK) then\r
-                               if FREQUENCY >= x"000002" then\r
-                                       frequency_i <= FREQUENCY-2 after 1 ns;\r
+                               if frequency_in >= x"000002" then\r
+                                       frequency_i <= frequency_in-2;\r
                                end if;\r
                        reset_delay <= RESET;   --I want the timer to start again after the operations with the frequency\r
       end if;\r
@@ -63,9 +74,9 @@ begin
                begin\r
                        if rising_edge(CLK) then\r
                                if reset_delay = '1' or last_timer = frequency_i or RESET = '1' then --was FREQUENCY\r
-                                       reset_counter <= '1' after 1 ns;\r
+                                       reset_counter <= '1';\r
                                else\r
-                                       reset_counter <= '0' after 1 ns;\r
+                                       reset_counter <= '0';\r
                                end if;      \r
       end if;\r
                end process;\r
@@ -84,19 +95,19 @@ last_timer <= timer when rising_edge(CLK);
                                \r
                                        when idle =>    \r
             PULSE <= "0000";\r
-            pulse_width_i <= PULSE_WIDTH;\r
+            pulse_width_i <= pulse_width_in;\r
             \r
-                                               if last_timer = x"000000" then\r
+                                               if last_timer = x"000000" and ENABLE = '1' then\r
                                                        state <= generate_pulse;\r
                                                end if;\r
                                                \r
                                        when generate_pulse =>\r
                                                if pulse_width_i = x"000002" then \r
-                                                       PULSE <= "0011" after 1 ns;\r
+                                                       PULSE <= "0011";\r
                                                elsif pulse_width_i = x"000003" then \r
-                                                       PULSE <= "0111" after 1 ns;\r
+                                                       PULSE <= "0111";\r
                                                elsif pulse_width_i >= x"000004" then \r
-                                                       PULSE <= "1111" after 1 ns; \r
+                                                       PULSE <= "1111"; \r
                                                else \r
                                                        PULSE <= "0001";\r
                                                end if;\r

diff --git a/pulser/trb3sc_pulser.lpf b/pulser/trb3sc_pulser.lpf
index feb616233eb31a25e83d610364eac93e6330734a..351506731d79a143c11f8682fcb99050747c9f66 100644 (file)
--- a/pulser/trb3sc_pulser.lpf
+++ b/pulser/trb3sc_pulser.lpf
@@ -8,10 +8,16 @@ MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_right 20 ns;
 MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_left  20 ns;
 
 
-BLOCK PATH TO CELL "THE_PULSER/period*" ;
-BLOCK PATH TO CELL "THE_PULSER/length*" ;
-BLOCK PATH TO CELL "THE_PULSER/offset*" ;
 
+BLOCK NET "THE_PULSER/period*" ;
+BLOCK NET "THE_PULSER/length*" ;
+BLOCK NET "THE_PULSER/offset*" ;
+BLOCK NET "THE_PULSER/pulser_reset*" ;
+BLOCK NET "THE_PULSER/pulser_enable*" ;
+
+CLOCK_TO_OUT "OUTP*" 30 NS CLKNET = "THE_PULSER/THE_LEFT_DDR/clkop";
+CLOCK_TO_OUT "OUTP*" 30 NS CLKNET = "THE_PULSER/THE_RIGHT_DDR/clkop";
+CLOCK_TO_OUT "SEL*" 40 NS CLKNET = "clk_sys";
 
 
 # REGION "REGION_PULSER_LEFT" "R2C2D" 114 36 DEVSIZE;