attilio

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index 6a0ecc8cfc4a9af1e2d9ea70c46c404857167611..f247dd6c4b79c72f08822d636853e787958dc5e4 100644 (file)
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -149,11 +149,12 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal pulse_trdyo_i      : std_logic;
   signal debug_trigger_distributor_i : std_logic_vector(31 downto 0);
   signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
-  signal pseudo_timing_trigger : std_logic;
+  signal pulse_pseudo_timing_trigger : std_logic;
   signal cal_trigger_register_in_i : std_logic_vector(15 downto 0);
   signal direction_data_line_in_i : std_logic_vector(3 downto 0);
   signal motherboard_type_in_i : std_logic_vector(3 downto 0);
-
+  signal pulse_begin_run_trigger_i : std_logic;
+  
 begin
 ---------------------------------------------------------------------
 -- PLL: 100 MHz
@@ -387,7 +388,8 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
       thresh_mem_write        <= '0';
       thresh_mem_read         <= '0';
 
-      if reg_REGIO_ADDR(15 downto 7) = x"A0"&'0' then
+--FEE control register
+      if reg_REGIO_ADDR(15 downto 12) = x"A" then
         thresh_mem_write           <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE;
         thresh_mem_read            <= reg_REGIO_READ;
         REGIO_DATA_IN(15 downto 0) <= thresh_mem_data_out;
@@ -496,32 +498,50 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
 ---------------------------------------------------------------------
 -- Transport trigger to FEE
 ---------------------------------------------------------------------
-
+-- 0xc0 0x0011 -> send begrun trigger to 1 short
+-- 0xc0 0x0021 -> send begrun trigger to 1 long
+-- 0xc0 0x0C10 -> x"C" set calibration trigger, x"0" normal 
+-- 0xc0 0x1000 -> send NORMAL trigger
+-- 0xc0 0x1C00 -> send CALIBRATION trigger
+  
   PROC_GEN_TIMING : process(CLK_100)
     begin
       if rising_edge(CLK_100) then
-      --  last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0);
-      --  pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
-        cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(7 downto 4);
-        motherboard_type_in_i <= REGIO_REGISTERS_OUT(11 downto 8);
+--pulse for BEGRUN trigger
+ --       last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0);
+ --       pulse_begin_run_trigger_i <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
+
+--FEE definition
+        motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);  
+        cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8);
 
       end if;
     end process;
 
+-------------------------------------------------------------------------------
+-- pulse for trigger (NORMAL/CAL)
+-------------------------------------------------------------------------------
     PULSE_TRIGGER : edge_to_pulse
+      port map (
+        CLOCK         => CLK_100,
+        ENABLE_CLK_IN => '1',
+        SIGNAL_IN     => REGIO_REGISTERS_OUT(12),
+        PULSE_OUT     => pulse_pseudo_timing_trigger);
+
+    PULSE_BEGRUN_TRIGGER : edge_to_pulse
       port map (
         CLOCK         => CLK_100,
         ENABLE_CLK_IN => '1',
         SIGNAL_IN     => REGIO_REGISTERS_OUT(0),
-        PULSE_OUT     => pseudo_timing_trigger);
+        PULSE_OUT     => pulse_begin_run_trigger_i);
 
     THE_TRIG_DISTR : trigger_distributor
-    port map (
+      port map (
         CLK                => CLK_100,
         RESET              => reset_internal,
-        INTERNAL_RESET_IN  => '0',
+        INTERNAL_RESET_IN  => pulse_begin_run_trigger_i,
         A_RDO_IN           => token_to_mux_out_i,
-        TRIGGER_IN         => pseudo_timing_trigger,
+        TRIGGER_IN         => pulse_pseudo_timing_trigger,
         TRIGGER_TYPE_IN    => LVL1_TRG_TYPE_OUT,
         INIT_ALL_BUSES_OUT => init_all_buses_i,
         ROC1_WRITTEN_IN    => roc1_written_i,