#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
#my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
-my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64';
# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/';
-my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
###################################################################################
#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 3 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+
execute($c);
# IOR IO Timing Report
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
-
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_noctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
attribute syn_useioff of FLASH_CS : signal is true;
attribute syn_useioff of FLASH_DIN : signal is true;
attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA1_COMM : signal is true;
- attribute syn_useioff of FPGA2_COMM : signal is true;
- attribute syn_useioff of FPGA3_COMM : signal is true;
- attribute syn_useioff of FPGA4_COMM : signal is true;
+ attribute syn_useioff of FPGA1_COMM : signal is false;
+ attribute syn_useioff of FPGA2_COMM : signal is false;
+ attribute syn_useioff of FPGA3_COMM : signal is false;
+ attribute syn_useioff of FPGA4_COMM : signal is false;
end entity;
clk_sys_internal <= CLK_GPLL_RIGHT;
clk_raw_internal <= CLK_GPLL_RIGHT;
clk_gbe_internal <= CLK_GPLL_RIGHT;
+ pll_lock <= '1';
end generate;
\r
MULTICYCLE TO CELL "THE_MEDIA_ONBOARD/SCI_DATA_OUT*" 50 ns;\r
MULTICYCLE TO CELL "gen_uplink_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_*io*" 20 ns;\r
+MULTICYCLE FROM CELL "THE_MEDIA_*_sfp_losio*" 20 ns;\r
\r
#SPI Interface\r
#REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r