]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
adapted trb3_gbe for trigger generation
authorJan Michel <j.michel@gsi.de>
Tue, 25 Mar 2014 15:36:06 +0000 (16:36 +0100)
committerJan Michel <j.michel@gsi.de>
Tue, 25 Mar 2014 15:39:50 +0000 (16:39 +0100)
trb3_gbe/compile_central_frankfurt.pl
trb3_gbe/trb3_central.prj
trb3_gbe/trb3_central.vhd
trb3_gbe/trb3_central_constraints.lpf

index c5e582fd5485105738c00cf8e98ed0a4295d31ac..404c50582d49560cb4068ee10fe42c29ef6cf0fa 100755 (executable)
@@ -10,9 +10,9 @@ use strict;
 #Settings for this project
 my $TOPNAME                      = "trb3_central";  #Name of top-level entity
 #my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
-my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/3.0_x64';
 # my $synplify_path                = '/d/jspc29/lattice/synplify/fpga_e201103/';
-my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $synplify_path                = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################
@@ -116,7 +116,9 @@ execute($c);
 
 
 #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 3 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+
 execute($c);
 
 # IOR IO Timing Report
index f46e1a0e0bccc894019a9832edddfa42ac60c023..4e74289c4670ddd124045f17be7efe5586d203a1 100644 (file)
@@ -218,7 +218,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd"
-
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_noctc.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
index 7588e4f5b3b582ecdbac821b17c7d39bbe0d7a3c..8b33b1de3f38406381e0d24bc87a970ad03cded9 100644 (file)
@@ -127,10 +127,10 @@ entity trb3_central is
     attribute syn_useioff of FLASH_CS           : signal is true;
     attribute syn_useioff of FLASH_DIN          : signal is true;
     attribute syn_useioff of FLASH_DOUT         : signal is true;
-    attribute syn_useioff of FPGA1_COMM         : signal is true;
-    attribute syn_useioff of FPGA2_COMM         : signal is true;
-    attribute syn_useioff of FPGA3_COMM         : signal is true;
-    attribute syn_useioff of FPGA4_COMM         : signal is true;
+    attribute syn_useioff of FPGA1_COMM         : signal is false;
+    attribute syn_useioff of FPGA2_COMM         : signal is false;
+    attribute syn_useioff of FPGA3_COMM         : signal is false;
+    attribute syn_useioff of FPGA4_COMM         : signal is false;
 
 
 end entity;
@@ -342,6 +342,7 @@ gen_125 : if USE_125_MHZ = c_YES generate
   clk_sys_internal <= CLK_GPLL_RIGHT;
   clk_raw_internal <= CLK_GPLL_RIGHT;
   clk_gbe_internal <= CLK_GPLL_RIGHT;
+  pll_lock         <= '1';
 end generate;
 
 
index c0bd043c7800ca0e13450226204b3df1c5ec3f43..8e919cc8bdddfde30304209a059d97f98d210705 100644 (file)
@@ -39,6 +39,8 @@ LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ;
 \r
 MULTICYCLE TO CELL "THE_MEDIA_ONBOARD/SCI_DATA_OUT*" 50 ns;\r
 MULTICYCLE TO CELL "gen_uplink_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_*io*" 20 ns;\r
+MULTICYCLE FROM CELL "THE_MEDIA_*_sfp_losio*" 20 ns;\r
 \r
 #SPI Interface\r
 #REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r