*** empty log message ***

diff --git a/daqnet.kilepr b/daqnet.kilepr
index 8467c4f66abd1a07f77fa294fd01fda175c2f140..25607a423be62ccca477092669692e2e13486522 100755 (executable)
--- a/daqnet.kilepr
+++ b/daqnet.kilepr
@@ -3,7 +3,7 @@ img_extIsRegExp=false
 img_extensions=.eps .jpg .jpeg .png .pdf .ps .fig .gif
 kileprversion=2
 kileversion=2.0
-lastDocument=gbe.tex
+lastDocument=main.tex
 masterDocument=main.tex
 name=trbnet
 pkg_extIsRegExp=false
@@ -15,6 +15,24 @@ src_extensions=.tex .ltx .latex .dtx .ins
 MakeIndex=
 QuickBuild=PDFLaTeX+ViewPDF
 
+[item:/local/trb/cvs/daq_docu/cts.tex]
+archive=true
+column=50
+encoding=ISO 8859-15
+highlight=LaTeX
+line=46
+open=true
+order=14
+
+[item:/local/trb/cvs/daq_docu/tof.tex]
+archive=true
+column=3
+encoding=ISO 8859-15
+highlight=LaTeX
+line=7
+open=true
+order=13
+
 [item:biblio.bib]
 archive=true
 column=0
@@ -44,19 +62,19 @@ order=11
 
 [item:gbe.tex]
 archive=true
-column=2
+column=191
 encoding=ISO 8859-15
 highlight=LaTeX
-line=53
+line=30
 open=true
 order=12
 
 [item:hubs.tex]
 archive=true
-column=186
+column=91
 encoding=
 highlight=LaTeX
-line=46
+line=65
 open=true
 order=6
 
@@ -80,10 +98,10 @@ order=2
 
 [item:main.tex]
 archive=true
-column=20
+column=10
 encoding=UTF-8
 highlight=LaTeX
-line=129
+line=101
 open=true
 order=0
 
@@ -125,10 +143,10 @@ order=7
 
 [item:slowcontrol.tex]
 archive=true
-column=121
+column=0
 encoding=UTF-8
 highlight=LaTeX
-line=115
+line=16
 open=true
 order=4
 

diff --git a/mdc.tex b/mdc.tex
index 2ba8832096860a04d08059dcff68d4d6ada8d92e..b7da3d752296239fe681139d160ec2c20c40905f 100755 (executable)
--- a/mdc.tex
+++ b/mdc.tex
@@ -97,7 +97,10 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr
 
 \subsubsection{MDC OEP Status Register}
 \begin{description}
- \item[0x9000: \filename{Tdc\_Readout} status register] The status register of the entity that reads data provided by the MBO.
+ \item[0x9000: \filename{Control} status register] 
+ \item[0x9001: \filename{Trigger\_Handler} status register]
+ \item[0x9002: \filename{Data\_Handler} status register] 
+ \item[0x9003: \filename{Tdc\_Readout} status register] The status register of the entity that reads data provided by the MBO.
   \begin{description}
    \item[Bit 3..0] State machine status \\ 0: idle; 1: save\_L\_word, 2: send\_token, 3: wait\_1, 4: wait\_2, 5: save\_L\_word\_next. 6: wait\_for\_AOD\_low, 7: wait\_3, 8: wait\_4, 9: save\_H\_word\_state\_next
    \item[Bit 4] Data valid out
@@ -107,7 +110,21 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr
    \item[Bit 8] \portname{A\_Reserve\_In}
    \item[Bit 12..9] Lower four bits of trigger number - used to tag data in fifos
   \end{description}
- \item[0x9001: \filename{Load\_Mode\_Line} status register] The status register of the entity that controls the mode lines to the MBO.
+ \item[0x9004: \filename{Control\_Line\_Handler} status register] 
+ \item[0x9005: \filename{Trigger\_Begrun} status register] The status register of the entity that controls the entities controlling mode lines and loading configuration to the MBO.
+  \begin{description}
+   \item[Bit 3..0] Step of the mode line loading sequence
+   \item[Bit 7..4] Step of the configuration loading sequence
+   \item[Bit 8] Start changing mode lines to begin calibration trigger
+   \item[Bit 9] Start configuration to begin calibration trigger
+   \item[Bit 10] Start changing mode lines for begin run trigger
+   \item[Bit 11] Start configuration for begin run trigger
+   \item[Bit 12] Configuration for calibration has been loaded
+   \item[Bit 13] Configuration for start-up has been loaded
+   \item[Bit 14] Configuration for start-up has been loaded
+   \item[Bit 19..16] Status of the state machine
+  \end{description}
+ \item[0x9006: \filename{Load\_Mode\_Line} status register] The status register of the entity that controls the mode lines to the MBO.
   \begin{description}
    \item[Bit 7..0] State machine status
    \item[Bit 8] MBO got the right sequence of modes for start-up
@@ -119,7 +136,7 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr
    \item[Bit 20] status of WRM line
    \item[Bit 21] status of RDM line
   \end{description}
- \item[0x9002: \filename{Load\_Tdc\_Setup} status register] The status register of the entity that loads data to TDC and CPLD configuration registers.
+ \item[0x9007: \filename{Load\_Tdc\_Setup} status register] The status register of the entity that loads data to TDC and CPLD configuration registers.
   \begin{description}
    \item[Bit 7..0] State machine status
    \item[Bit 17..8] Current address of configuration RAM read pointer
@@ -127,18 +144,6 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr
    \item[Bit 19] Loading second part of configuration during calibration
    \item[Bit 20] Processing a calibration trigger
   \end{description}
- \item[0x9003: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
- \item[0x9004: \filename{Trigger\_Begrun} status register] The status register of the entity that controls the entities controlling mode lines and loading configuration to the MBO.
-  \begin{description}
-   \item[Bit 3..0] Step of the mode line loading sequence
-   \item[Bit 7..4] Step of the configuration loading sequence
-   \item[Bit 8] Start changing mode lines to begin calibration trigger
-   \item[Bit 9] Start configuration to begin calibration trigger
-   \item[Bit 10] Start changing mode lines for begin run trigger
-   \item[Bit 11] Start configuration for begin run trigger
-   \item[Bit 12] Configuration for calibration has been loaded
-   \item[Bit 13] Configuration for start-up has been loaded
-   \item[Bit 14] Configuration for start-up has been loaded
-   \item[Bit 19..16] Status of the state machine
-  \end{description}
+ \item[0x9008: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
 \end{description}
+

diff --git a/showerdata.tex b/showerdata.tex
index c68308d02ed3bc161d73a52034377333073ec606..2a9826a437960b4439c200b6e6e21f712e2148fa 100755 (executable)
--- a/showerdata.tex
+++ b/showerdata.tex
@@ -8,7 +8,7 @@ The data format generated by Shower is based on its physical structure: 32 colum
 
 The different parts of data (pad address and ADC data) is packed into one 32 bit data word as shown in table \ref{showerdatanormal}. If a data word is viewed in raw hex format, the different parts can easily be recognized due to the nibble boundaries involved:  $0xPRRCCDDD$ where D is data, C is column, R is row and P is plane. A structure for debug and status words is not yet set up. 
 
-\begin{table}
+\begin{table}[bp]
 \begin{center}
 \begin{tabularx}{\textwidth}{|c|C|C|C|}
 \hline

diff --git a/slowcontrol.tex b/slowcontrol.tex
index 8a9d71ebe7e68669ee917a31b6c4dd53ac266dd7..841a517f73e1ff21ab8721cb2ac62e4e6fe57ea9 100755 (executable)
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -251,21 +251,21 @@ E000 -- FFFF & Debugging & Memories and Registers for Debugging \\
 \end{table}
 
 
-\paragraph{Common Control and Status Registers}
+\paragraph{Common Control and Status Registers (0x00 - 0x01, 0x20 - 0x22)}
 
-The first common status register is described in table \ref{CommonStatReg0}. It is used for error flags 
-and readback of the boards temperature. The second status register is used to read the LVL1 trigger number 
+The first common status register (0x00) is described in table \ref{CommonStatReg0}. It is used for error flags 
+and readback of the boards temperature. The second status register (0x01) is used to read the LVL1 trigger number 
 of the last timing trigger (Bits 15 -- 0) and the number of the event last read on the IPU channel 
 (Bits 31 -- 16).
 
-\noindent The first common control register consists of strobe signals for dummy timing triggers and reset 
+\noindent The first common control register (0x20) consists of strobe signals for dummy timing triggers and reset 
 signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a 
 delay of about 3~us has to be included to allow the endpoint to send back a correct answer. 
 
-\noindent The second common control register is used to set the current LVL1 trigger number (Bits 15 -- 0) 
+\noindent The second common control register (0x21) is used to set the current LVL1 trigger number (Bits 15 -- 0) 
 and the number of received timing triggers (Bits 31-16). 
 
-\noindent The third control register includes frontend enable bits (Bits 15 -- 0), as well as a trigger 
+\noindent The third control register (0x22) includes frontend enable bits (Bits 15 -- 0), as well as a trigger 
 enable bit (Bit 31), a debug enable bit (Bit 30), and three data format bits for general usage (Bits 23 -- 20). 
 A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 
@@ -329,11 +329,11 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 \hline
 \textbf{Bits} & \textbf{Description} \\
 \hline\hline
-0 -- 15 & reset frontends \\
+0 -- 15 & front-end enable \\
 16 -- 19 & reserved \\
-20 -- 23 & data format \\
-24 - 29 & reserved \\
-30 & enable debug \\
+20 -- 23 & data format select \\
+24 -- 29 & reserved \\
+30 & enable debug output \\
 31 & enable trigger \\
 \hline
 \end{tabular}
@@ -368,6 +368,7 @@ This register holds information about the type of hardware. The upper 16 bit def
 4210 & Shower AddOn version 2 FPGA 1 \\
 4220 & Shower AddOn version 2 FPGA 2 \\
 4230 & Shower AddOn version 2 FPGA 3 \\
+5000 & Old CTS \\
 5100 & CTS AddOn FPGA 1 \\
 5200 & CTS AddOn FPGA 2 \\
 6100 & Hub AddOn version 1 \\