SCI problem tracked down, but not solved

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 187e9c4fec61076d83e03c71663e51de5a872a62..42879e14ec2be74cb9cd98ad82971888d992d2eb 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -550,8 +550,6 @@ end generate;
       SCI_WR      => sci_write_i,
       -- WAP
       WA_POS_OUT  => wa_position_i,
-      WA_READ_OUT => open,
-      LINK_RX_READY_IN => '0', -- NOT REALLY NEEDED
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,

diff --git a/media_interfaces/sync/sci_reader.vhd b/media_interfaces/sync/sci_reader.vhd
index 79221ae4b6bcc2ec98267da9d148229c956c2bb8..e156c7e9b33b9642ddb7b8baa7760a9fc60b1dea 100644 (file)
--- a/media_interfaces/sync/sci_reader.vhd
+++ b/media_interfaces/sync/sci_reader.vhd
@@ -142,7 +142,7 @@ begin
       sci_state       <= GET_WA_FINISH;
     when GET_WA_FINISH =>
       wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
-      sci_state       <= GET_WA;    
+      sci_state       <= GET_WA;
       cnt             := cnt + 1;
   end case;
   

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 0f99fcea9c303b08dbda5ab7287df1c478ebffca..0dfe76614508643b89cb5acc06c06dac72a4986b 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -23,8 +23,6 @@ entity sci_reader_RS is
     SCI_WR           : out std_logic;
     
     WA_POS_OUT       : out std_logic_vector(15 downto 0);
-    WA_READ_OUT      : out std_logic;
-    LINK_RX_READY_IN : in  std_logic;
     
     --Slowcontrol
     BUS_RX           : in  CTRLBUS_RX;
@@ -45,7 +43,6 @@ signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
 signal wa_position       : std_logic_vector(15 downto 0);
 signal next_sci_wr       : std_logic;
-signal wa_read_i         : std_logic;
 
 begin
 
@@ -75,7 +72,6 @@ begin
       SCI_RD      <= '0';
       next_sci_wr <= '0';
       sci_timer   <= sci_timer + 1;
-      wa_read_i   <= '0';
       if BUS_RX.read = '1' or BUS_RX.write = '1' then
         SCI_SEL(0)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
         SCI_SEL(1)    <=     BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
@@ -88,10 +84,9 @@ begin
         SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
         next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
         sci_state     <= SCTRL;
-      elsif (sci_timer(sci_timer'left) = '1') and (LINK_RX_READY_IN = '0') then
-        sci_timer     <= (others => '0');
-        sci_state     <= GET_WA;
-        wa_read_i     <= '1';
+--      elsif sci_timer(sci_timer'left) = '1' then
+--        sci_timer     <= (others => '0');
+--        sci_state     <= GET_WA;
       end if;      
     when SCTRL =>
       if sci_reg_i = '1' then
@@ -120,7 +115,6 @@ begin
         sci_state     <= IDLE;
       else
         sci_state     <= GET_WA_WAIT;
-        wa_read_i     <= '1';
         if FPGA_TYPE = 3 then
           SCI_ADDR      <= "100010";--'0' & x"22"; --for ECP3
         elsif FPGA_TYPE = 5 then
@@ -132,14 +126,11 @@ begin
       end if;
     when GET_WA_WAIT  =>
       sci_state       <= GET_WA_WAIT2;
-      wa_read_i       <= '1';
     when GET_WA_WAIT2 =>
       sci_state       <= GET_WA_FINISH;
-      wa_read_i       <= '1';
     when GET_WA_FINISH =>
       wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
-      sci_state       <= GET_WA; 
-      wa_read_i       <= '1';   
+      sci_state       <= GET_WA;
       cnt             := cnt + 1;
   end case;
   
@@ -149,6 +140,4 @@ begin
   
 end process;
 
-WA_READ_OUT <= wa_read_i;
-
 end architecture;