A bit of clean-up in the repo

diff --git a/.gitignore b/.gitignore
index 6b8589cde7877698ea40763b0d6c987cc695bcfc..d7cc176ab3ad770ab691a6fe9ae3500101c2ac95 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -36,3 +36,4 @@ work
 licbug.txt
 **/*workdir
 **/diamond
+config_compile.pl

diff --git a/32PinAddOn/config_compile.pl b/32PinAddOn/config_compile.pl
deleted file mode 120000 (symlink)
index 67b86a0..0000000
--- a/32PinAddOn/config_compile.pl
+++ /dev/null
@@ -1 +0,0 @@
-config_compile_gsi.pl
\ No newline at end of file

diff --git a/32PinAddOn/config_compile_frankfurt.pl b/32PinAddOn/config_compile_frankfurt.pl
new file mode 100644 (file)
index 0000000..8bf794b
--- /dev/null
+++ b/32PinAddOn/config_compile_frankfurt.pl
@@ -0,0 +1,21 @@
+TOPNAME                      => "trb3_periph_32PinAddOn",
+project_path                 => "32PinAddOn",
+lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@jspc29",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.7_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
+# synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+synplify_command             => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3/32PinAddOn/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3_periph_32PinAddOn.prj\" #",
+
+
+nodelist_file                => '../nodes_lxhadeb07.txt',
+par_options                  => '../../base/trb3_periph.p2t',
+    
+#Include only necessary lpf files
+include_TDC                  => 1,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,

diff --git a/blank/config_compile_frankfurt.pl b/blank/config_compile_frankfurt.pl
index 9465dc12c64681c936370c8eacf21038740045bf..9f8f8e09d09e49b0ddb2a2de18a7922a63b046a2 100644 (file)
--- a/blank/config_compile_frankfurt.pl
+++ b/blank/config_compile_frankfurt.pl
@@ -1,9 +1,9 @@
 TOPNAME                      => "trb3_periph_blank",
-lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.8_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+#synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/bin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodes_frankfurt.txt',
@@ -21,4 +21,4 @@ twr_number_of_errors         => 20,
 Familyname  => 'LatticeECP3',
 Devicename  => 'LFE3-150EA',
 Package     => 'FPBGA672',
-Speedgrade  => '8',
\ No newline at end of file
+Speedgrade  => '8',

diff --git a/blank/project/trb3_periph_blank.ldf b/blank/project/trb3_periph_blank.ldf
index 99c006bfd8063e4ef78fdafd21793a8e85f190a5..d4d93735ee37718feebbc7002a0a263b500b24f0 100644 (file)
--- a/blank/project/trb3_periph_blank.ldf
+++ b/blank/project/trb3_periph_blank.ldf
@@ -1,107 +1,299 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <BaliProject version="3.2" title="blank" device="LFE3-150EA-8FN672C" default_implementation="trb3_periph_blank">
     <Options/>
-    <Implementation title="trb3_periph_blank" dir="trb3_periph_blank" description="Automatically generated implemenatation" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_blank">
-            <Option name="top" value="trb3_periph_blank" />
-        </Options>
-        <Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../config.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_regio_bus_handler_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/bus_register_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trb3/base/code/trb3_tools.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trb3sc/code/lcd.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trb3sc/code/debuguart.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/uart.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../base/code/input_statistics.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../base/code/sedcheck.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../trb3_periph_blank.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
+    <Implementation title="trb3_periph_blank" dir="trb3_periph_blank" description="Automatically generated implemenatation" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="edge_to_pulse" top="trb3_periph_blank"/>
+        <Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../config.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_regio_bus_handler_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/bus_register_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/code/trb3_tools.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trb3sc/code/lcd.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trb3sc/code/debuguart.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/uart.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/code/input_statistics.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../base/code/sedcheck.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../trb3_periph_blank.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work" top_module="trb3_periph_blank"/>
+        </Source>
         <Source name="../workdir/trb3_periph_blank.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>

diff --git a/blank/trb3_periph_blank.prj b/blank/trb3_periph_blank.prj
index 1d97dbc5b62fc8ccf11f2e254a293ff42b0a06ef..a440e0733efd29bfd737fdd8c6155771cefe064a 100644 (file)
--- a/blank/trb3_periph_blank.prj
+++ b/blank/trb3_periph_blank.prj
@@ -132,6 +132,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"

diff --git a/trb3_gbe/config_compile.pl b/trb3_gbe/config_compile.pl
deleted file mode 120000 (symlink)
index 4d057e6..0000000
--- a/trb3_gbe/config_compile.pl
+++ /dev/null
@@ -1 +0,0 @@
-./config_compile_gsi.pl
\ No newline at end of file