add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_RS.vhd"
#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"
+
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
signal tx_dlm_i : std_logic;
signal rx_dlm_i : std_logic;
+ signal destroy_link_i : std_logic;
+
begin
---------------------------------------------------------------------------
DEBUG_OUT => debug_clock_reset
);
+-- Reset by GbE: a minimum delay of 1us is kept before the reset
+-- pulse is injected into the reset handler.
proc_make_reset : process begin
wait until rising_edge(clk_sys);
- if(reset_via_gbe = '1') then
+ if( reset_via_gbe = '1' ) then
reset_via_gbe_long <= '1';
reset_via_gbe_timer <= '1';
end if;
- if timer.tick_us = '1' then
+ if( timer.tick_us = '1' ) then
reset_via_gbe_timer <= '0';
reset_via_gbe_long <= reset_via_gbe_timer;
end if;
-- PCSB Downlink without backplane is SFP
---------------------------------------------------------------------------
gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
- THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_RS
- generic map(
- SERDES_NUM => 3,
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection
- MEDIA_MED2INT => med2int(0),
- MEDIA_INT2MED => int2med(0),
- --Sync operation
- RX_DLM_OUT => rx_dlm_i,
- RX_DLM_WORD_OUT => open,
- TX_DLM_IN => tx_dlm_i,
- TX_DLM_WORD_IN => x"aa",
- --SFP Connection
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TX_DIS(1),
- --Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open
- );
+
+THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS
+ generic map(
+ IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER)
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection TX/RX
+ MEDIA_MED2INT(3) => med2int(0),
+ MEDIA_INT2MED(3) => int2med(0),
+ --Sync operation
+ RX_DLM_OUT(2 downto 0) => open,
+ RX_DLM_OUT(3) => rx_dlm_i,
+ RX_DLM_WORD_OUT(2 downto 0) => open,
+ RX_DLM_WORD_OUT(3) => open,
+ TX_DLM_IN(2 downto 0) => (others => '0'),
+ TX_DLM_IN(3) => tx_dlm_i,
+ TX_DLM_WORD_IN => x"aa_aa_aa_aa",
+ WORD_SYNC_IN => '1',
+ WORD_SYNC_OUT => open,
+ SYNC_TX_PLL_IN => clk_full_osc,
+ SYNC_TX_PLL_OUT => open,
+ DESTROY_LINK_IN(2 downto 0) => (others => '0'),
+ DESTROY_LINK_IN(3) => destroy_link_i,
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => '1',
+ SD_LOS_IN(0) => '1',
+ SD_TXDIS_OUT(0) => open,
+ SD_PRSNT_N_IN(1) => '1',
+ SD_LOS_IN(1) => '1',
+ SD_TXDIS_OUT(1) => open,
+ SD_PRSNT_N_IN(2) => '1',
+ SD_LOS_IN(2) => '1',
+ SD_TXDIS_OUT(2) => open,
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ --Control Interface
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
+ -- Status and control port
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open
+ );
+
+-- THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_RS
+-- generic map(
+-- SERDES_NUM => 3,
+-- IS_SYNC_SLAVE => c_NO
+-- )
+-- port map(
+-- CLK_REF_FULL => clk_full_osc,
+-- CLK_INTERNAL_FULL => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- --Internal Connection
+-- MEDIA_MED2INT => med2int(0),
+-- MEDIA_INT2MED => int2med(0),
+-- --Sync operation
+-- RX_DLM_OUT => rx_dlm_i,
+-- RX_DLM_WORD_OUT => open,
+-- TX_DLM_IN => tx_dlm_i,
+-- TX_DLM_WORD_IN => x"aa",
+-- DESTROY_LINK_IN => destroy_link_i,
+-- --SFP Connection
+-- SD_PRSNT_N_IN => SFP_MOD0(1),
+-- SD_LOS_IN => SFP_LOS(1),
+-- SD_TXDIS_OUT => SFP_TX_DIS(1),
+-- --Control Interface
+-- BUS_RX => bussci2_rx,
+-- BUS_TX => bussci2_tx,
+-- -- Status and control port
+-- STAT_DEBUG => open,
+-- CTRL_DEBUG => open
+-- );
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
THE_SYNC_PROC: process( clk_sys )
HDR_IO(2) <= rx_dlm_i;
HDR_IO(1) <= tx_dlm_i;
+ destroy_link_i <= common_ctrl_reg(88);
+
end generate;
---------------------------------------------------------------------------