changed for new protocol between vulom and cts

diff --git a/trb_cts/cts.vhd b/trb_cts/cts.vhd
index e3de16d8acd7e498bd347e7f258e7ee3601bd577..0d05422a49f15f0019c7e253ca5aac39a00e5adc 100644 (file)
--- a/trb_cts/cts.vhd
+++ b/trb_cts/cts.vhd
@@ -274,6 +274,8 @@ architecture cts of cts is
       RESET              : in  std_logic;
       DATA_IN            : in  std_logic_vector(1 downto 0);
       BUSY               : out std_logic;
+      ACK_TO_VULOM       : out std_logic;
+      ERR_TO_VULOM       : out std_logic;
       API_DATA           : out std_logic_vector(47 downto 0);
       API_RUN_OUT        : in  std_logic;
       API_SHORT_TRANSFER : out std_logic;
@@ -737,46 +739,46 @@ begin
           end if;                 
         end if;
       end process COUNTER_FOR_API;
--------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
 -- media to api, api to media
--------------------------------------------------------------------------------
-     TLK_RX_CLK_BUFR: BUFR
-       port map(
-         CE => '1',
-         CLR => '0',
-         I => TLK_RX_CLK,
-         O => tlk_rx_clk_r
-         );
-      TLK_CLK_BUFR: BUFR
-        port map(
-          CE => '1',
-          CLR => '0',
-          I => TLK_CLK,
-          O => tlk_clk_r
-          );
-     SFP_TX_DIS  <= '0';
-     OPTICAL_MEDIA_TO_FROM_API: trbv2_tlk_api
-       port map (
-           RESET               => external_reset_i,
-           CLK                 => CLK,
-           TLK_CLK             => tlk_clk_r,
-           TLK_ENABLE          => TLK_ENABLE,
-           TLK_LCKREFN         => TLK_LCKREFN,
-           TLK_LOOPEN          => TLK_LOOPEN,
-           TLK_PRBSEN          => TLK_PRBSEN,
-           TLK_RXD             => TLK_RXD,
-           TLK_RX_CLK          => tlk_rx_clk_r,
-           TLK_RX_DV           => TLK_RX_DV,
-           TLK_RX_ER           => TLK_RX_ER,
-           TLK_TXD             => TLK_TXD,
-           TLK_TX_EN           => TLK_TX_EN,
-           TLK_TX_ER           => TLK_TX_ER,
-           DATA_OUT            => media_data_out_i,
-           DATA_IN             => media_data_in_i,
-           DATA_VALID_IN       => media_data_valid_in_i,
-           DATA_VALID_OUT      => media_data_valid_out_i,
-           TLK_API_REGISTER_00 => tlk_api_register_00_i);
-     fpga_register_0a_i <= media_data_valid_in_i & media_data_valid_out_i & media_data_out_i & media_data_in_i(13 downto 0);
+-----------------------------------------------------------------------------
+--      TLK_RX_CLK_BUFR: BUFR
+--        port map(
+--          CE => '1',
+--          CLR => '0',
+--          I => TLK_RX_CLK,
+--          O => tlk_rx_clk_r
+--          );
+--       TLK_CLK_BUFR: BUFR
+--         port map(
+--           CE => '1',
+--           CLR => '0',
+--           I => TLK_CLK,
+--           O => tlk_clk_r
+--           );
+--      SFP_TX_DIS  <= '0';
+--      OPTICAL_MEDIA_TO_FROM_API: trbv2_tlk_api
+--        port map (
+--            RESET               => external_reset_i,
+--            CLK                 => CLK,
+--            TLK_CLK             => tlk_clk_r,
+--            TLK_ENABLE          => TLK_ENABLE,
+--            TLK_LCKREFN         => TLK_LCKREFN,
+--            TLK_LOOPEN          => TLK_LOOPEN,
+--            TLK_PRBSEN          => TLK_PRBSEN,
+--            TLK_RXD             => TLK_RXD,
+--            TLK_RX_CLK          => tlk_rx_clk_r,
+--            TLK_RX_DV           => TLK_RX_DV,
+--            TLK_RX_ER           => TLK_RX_ER,
+--            TLK_TXD             => TLK_TXD,
+--            TLK_TX_EN           => TLK_TX_EN,
+--            TLK_TX_ER           => TLK_TX_ER,
+--            DATA_OUT            => media_data_out_i,
+--            DATA_IN             => media_data_in_i,
+--            DATA_VALID_IN       => media_data_valid_in_i,
+--            DATA_VALID_OUT      => media_data_valid_out_i,
+--            TLK_API_REGISTER_00 => tlk_api_register_00_i);
+--      fpga_register_0a_i <= media_data_valid_in_i & media_data_valid_out_i & media_data_out_i & media_data_in_i(13 downto 0);
 -------------------------------------------------------------------------------
 -- Vulom interafce
 -------------------------------------------------------------------------------
@@ -786,7 +788,9 @@ begin
          DATA_CLK           => ADDON_CLK2,
          RESET              => external_reset_i,
          DATA_IN            => ADO_TTL(3 downto 2),  --lvds_add_on_data (3 downto 0),
-         BUSY               => ADO_TTL(4),  --lvds_add_on_data (4),
+         BUSY               => open,  --lvds_add_on_data (4),
+         ACK_TO_VULOM       => ADO_TTL(5),
+         ERR_TO_VULOM       => ADO_TTL(6),
          API_DATA           => open,
          API_RUN_OUT        => apl_run_out_i,
          API_SHORT_TRANSFER => open,
@@ -946,9 +950,9 @@ begin
      --apl_seqnr_out_i;
      fpga_register_03_i <= x"bacd0000";--med_data_out_i_saved(31 downto 0);
      fpga_register_04_i <= x"00001234";--med_data_out_i_saved(63 downto 32);
-     ADO_TTL(5)<=  vulom_int_reg_00(0);
-     ADO_TTL(6) <= vulom_int_reg_00(1);--K_RX_ER;
-     ADO_TTL(7) <= ADDON_CLK1;--vulom_int_reg_00(2);
+--      ADO_TTL(5)<=  vulom_int_reg_00(0);
+--      ADO_TTL(6) <= vulom_int_reg_00(1);--K_RX_ER;
+--     ADO_TTL(7) <= ADDON_CLK1;--vulom_int_reg_00(2);
      SYNCH_RESET: process (CLK)
      begin  -- process SYNCH_RESET
        if rising_edge(CLK) then  -- rising clock edge