end process STATE_MEM;\r
\r
-- state transitions\r
-STATE_TRANSFORM: process( current_state, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN )\r
+STATE_TRANSFORM: process( current_state, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN, STX_TOC_IN )\r
begin\r
next_state <= IDLE; -- avoid latches\r
fifo_rst_x <= '0';\r
signal crc_reset : std_logic;
-- gk 05.10.10
-signal start_toc : std_logic_vector(7 downto 0);
+signal start_toc : unsigned(7 downto 0);
signal start_toc_c : std_logic;
begin
THE_FIFO_INHIBIT_PROC: process( CLK_IN )
begin
if( rising_edge(CLK_IN) ) then
- if ( (RESET_IN = '1') or (comma_stx = '1') or (ENABLE_CORRECTION_IN = '0') or (start_toc_c = '1') )then -- gk 05.10.10
+ if ( (RESET_IN = '1') or (comma_stx = '1') or (ENABLE_CORRECTION_IN = '0') )then -- gk 05.10.10
fifo_inhibit <= '0';
elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' )
- or (crc_match = '0' and comma_crc_x = '1' and crc_active = '1')
+ or ((crc_match = '0' or buf_rx_cv = '1') and comma_crc_x = '1' and crc_active = '1')
or c_invalid_k_x = '1'
or START_GONE_WRONG_IN = '1' then
fifo_inhibit <= '1';
START_TOC_PROC : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
- if (RESET_IN = '1') or (fifo_inhibit = '0') then
+ if (RESET_IN = '1') or (fifo_inhibit = '0') or start_toc_c = '1' then
start_toc <= (others => '0');
elsif (fifo_inhibit = '1') and (comma_stx = '0') then
- start_toc <= start_toc + x"1";
- end if;
+ start_toc <= start_toc + to_unsigned(1,1);
+ end if;
end if;
end process START_TOC_PROC;
-- gk 05.10.10
-start_toc_c <= '1' when (start_toc >= x"c8") else '0';
+start_toc_c <= '1' when (start_toc >= to_unsigned(200,8)) else '0';
-- gk 05.10.10
START_TOC_OUT_PROC : process(CLK_IN)
);
crc_reset <= RESET_IN or (fifo_inhibit and not comma_stx) or (not crc_active and not comma_crc);
- crc_enable <= (not buf_rx_k and not (comma_idle_x or comma_error_x or comma_stx_x or comma_crc_x)) or comma_crc_x;
+ crc_enable <= ((not buf_rx_k and not (comma_idle_x or comma_error_x or comma_stx_x or comma_crc_x)) or comma_crc_x) and not buf_rx_cv;
----------------------------------------------------------------------
RX_POSITION_OUT : out std_logic_vector(7 downto 0);\r
LD_START_POSITION_OUT : out std_logic;\r
START_POSITION_OUT : out std_logic_vector(7 downto 0);\r
+ START_GONE_WRONG_IN : in std_logic;\r
+ START_TIMEOUT_OUT : out std_logic;\r
-- Check\r
COMMA_LOCKED_OUT : out std_logic;\r
-- reset handling\r
PKT_TOC_IN : in std_logic; -- full packet RX timeout\r
RX_IC_IN : in std_logic; -- illegal comma or CodeViolation on RX\r
STX_FND_IN : in std_logic; -- StartOfTransmission found on RX\r
+ STX_TOC_IN : in std_logic; -- timeout waiting for StartOfTransmission\r
PKT_IN_TRANS_IN : in std_logic; -- paket in transmission to media interface\r
-- control signals\r
FIFO_RST_OUT : out std_logic; -- clear RX FIFO\r
signal statreg_rxcommahandler : std_logic_vector(15 downto 0);\r
signal statreg_rxchecker : std_logic_vector(15 downto 0);\r
\r
+signal start_position_mismatch : std_logic;\r
+signal start_position_mismatch_x : std_logic;\r
+signal req_position_buffer : std_logic_vector(7 downto 0);\r
\r
+signal stx_toc_found_x : std_logic;\r
+signal stx_toc_found : std_logic;\r
\r
begin\r
\r
RX_POSITION_OUT => rx_position,\r
LD_START_POSITION_OUT => start_retransmit_x,\r
START_POSITION_OUT => start_position,\r
+ START_GONE_WRONG_IN => start_position_mismatch,\r
+ START_TIMEOUT_OUT => stx_toc_found_x,\r
-- Check\r
COMMA_LOCKED_OUT => comma_locked,\r
-- reset handling\r
DEBUG_OUT => debug_rch\r
);\r
\r
+-- clock domain transfer for restart gone wrong\r
+THE_STX_PULSE_SYNC: pulse_sync\r
+port map(\r
+ CLK_A_IN => SYSCLK_IN,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => start_position_mismatch_x,\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => start_position_mismatch\r
+);\r
+\r
+-- clock domain transfer for internal RX data counter\r
+THE_STX_TOC_PULSE_SYNC: pulse_sync\r
+port map(\r
+ CLK_A_IN => CLK_IN,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => stx_toc_found_x,\r
+ CLK_B_IN => SYSCLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => stx_toc_found\r
+);\r
+\r
-- clock domain transfer for internal RX data counter\r
THE_LD_PULSE_SYNC: pulse_sync\r
port map(\r
-- Status signals\r
RX_ALLOW_IN => RX_ALLOW_IN,\r
RX_RESUME_IN => rx_resume,\r
- RX_LD_DATA_CTR_IN => ld_rx_position,\r
+ RX_LD_DATA_CTR_IN => '0', --ld_rx_position,\r
RX_DATA_CTR_VAL_IN => rx_position,\r
RX_DATA_CTR_OUT => request_position,\r
PACKET_TIMEOUT_OUT => packet_timeout,\r
RX_IC_IN => rx_gone_wrong,\r
STX_FND_IN => ld_rx_position,\r
PKT_IN_TRANS_IN => pkt_in_transit,\r
+ STX_TOC_IN => stx_toc_found,\r
-- control signals\r
FIFO_RST_OUT => fifo_rst,\r
RESUME_OUT => rx_resume,\r
DBG_OUT => debug_rxc\r
);\r
\r
+\r
+----------------------------------------------------------------------\r
+-- Check start\r
+----------------------------------------------------------------------\r
+process(SYSCLK_IN)\r
+ begin\r
+ if rising_edge(SYSCLK_IN) then\r
+ start_position_mismatch_x <= '0';\r
+ if request_retransmit = '1' then\r
+ req_position_buffer <= request_position;\r
+ elsif ld_rx_position = '1' then\r
+ if req_position_buffer /= rx_position then\r
+ start_position_mismatch_x <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
----------------------------------------------------------------------\r
-- Debug signals\r
----------------------------------------------------------------------\r
end if;
end process;
-ct_fifo_reset <= not tx_allow_qtx;
-TX_READ_OUT <= buf_tx_read_out;
+ ct_fifo_reset <= not tx_allow_qtx;
+ TX_READ_OUT <= buf_tx_read_out;
-ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN;
-ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
+ ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;
+ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
--- gk 05.10.10
-save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
-save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
+ -- gk 05.10.10
+ save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
+ save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
----------------------------------------------------------------------
-- RAM
-- gk 05.10.10
CRC_CALC : trb_net_CRC8
- port map(
- CLK => TXCLK_IN,
- RESET => crc_reset,
- CLK_EN => crc_en,
- DATA_IN => crc_data,
- CRC_OUT => crc_q,
- CRC_match => open
- );
+ port map(
+ CLK => TXCLK_IN,
+ RESET => crc_reset,
+ CLK_EN => crc_en,
+ DATA_IN => crc_data,
+ CRC_OUT => crc_q,
+ CRC_match => open
+ );
----------------------------------------------------------------------
STAT_REG_OUT(19) <= TX_ALLOW_IN;
STAT_REG_OUT(20) <= make_restart_i;
STAT_REG_OUT(21) <= make_request_i;
- STAT_REG_OUT(31 downto 22) <= (others => '0');
+ STAT_REG_OUT(22) <= load_eop;
+ STAT_REG_OUT(31 downto 23) <= (others => '0');
end if;
end process;
UNIFORM(seed1, seed2, rand);
int_rand := INTEGER(TRUNC(rand * 1000000.0));
- if( (int_rand MOD 100) = 0 ) then
+ if( (int_rand MOD 1000) = 0 ) then
buf_RX1_CV_OUT <= not RX1_CV_IN;
assert false report "RX1_CV" severity note;
wait for 40 ns;
-- end process;
--- RD1_DATA_proc : process
--- variable seed1 : positive;
--- variable seed2 : positive := 3;
--- variable rand : real;
--- variable int_rand : integer;
--- begin
---
--- wait until rising_edge(RXCLK_IN);
---
--- UNIFORM(seed1, seed2, rand);
--- int_rand := INTEGER(TRUNC(rand * 256.0));
---
--- if( (int_rand MOD 40) = 0 ) then
---
--- UNIFORM(seed1, seed2, rand);
--- int_rand := INTEGER(TRUNC(rand * 256.0));
---
--- buf_RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8);
---
--- assert false report "RX1_DATA" severity note;
---
--- wait for 40 ns;
--- buf_RX1_DATA_OUT <= RX1_DATA_IN;
--- else
--- buf_RX1_DATA_OUT <= RX1_DATA_IN;
--- end if;
---
--- wait for 400 ns;
---
--- end process;
+RD1_DATA_proc : process
+variable seed1 : positive;
+variable seed2 : positive := 3;
+variable rand : real;
+variable int_rand : integer;
+begin
+
+ wait until rising_edge(RXCLK_IN);
+
+ UNIFORM(seed1, seed2, rand);
+ int_rand := INTEGER(TRUNC(rand * 1000000.0));
+
+ if( (int_rand MOD 200) = 0 ) then
+
+ UNIFORM(seed1, seed2, rand);
+ int_rand := INTEGER(TRUNC(rand * 256.0));
+
+ buf_RX1_DATA_OUT <= RX1_DATA_IN;
+ buf_RX1_DATA_OUT(int_rand mod 8) <= not RX1_DATA_IN(int_rand mod 8);
+
+ assert false report "RX1_DATA" severity note;
+
+ wait for 40 ns;
+ buf_RX1_DATA_OUT <= RX1_DATA_IN;
+ else
+ buf_RX1_DATA_OUT <= RX1_DATA_IN;
+ end if;
+
+
+end process;
process
begin
wait until rising_edge(RXCLK_IN);
- buf_RX1_DATA_OUT <= RX1_DATA_IN;
+-- buf_RX1_DATA_OUT <= RX1_DATA_IN;
buf_RX1_K_OUT <= RX1_K_IN;
end process;
RESET_IN : in std_logic;
TX_DATA_IN : in std_logic_vector(15 downto 0);
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
TX_WRITE_IN : in std_logic;
TX_READ_OUT : out std_logic;
signal rx2_cv_in : std_logic := '0';
signal rx2_allow_in : std_logic := '0';
+ signal tx1_packet_num_in : std_logic_vector(2 downto 0);
+ signal tx2_packet_num_in : std_logic_vector(2 downto 0);
signal tx1_request_retransmit_in : std_logic := '0';
signal tx1_request_position_in : std_logic_vector( 7 downto 0) := (others => '0');
wait until rising_edge(clk); wait for 1 ns;
rx1_allow_in <= '1';
rx2_allow_in <= '1';
- wait for 2050 ns;
+ wait for 3050 ns;
wait until rising_edge(clk); wait for 1 ns;
tx1_allow_in <= '1';
tx2_allow_in <= '1';
RESET_IN => reset,
TX_DATA_IN => tx1_data_in,
+ TX_PACKET_NUMBER_IN => tx1_packet_num_in,
TX_WRITE_IN => tx1_write_in,
TX_READ_OUT => tx1_read_out,
RESET_IN => reset,
TX_DATA_IN => tx2_data_in,
+ TX_PACKET_NUMBER_IN => tx2_packet_num_in,
TX_WRITE_IN => tx2_write_in,
TX_READ_OUT => tx2_read_out,
MED_READ_OUT => open,
MED_DATAREADY_OUT => tx1_write_in,
MED_DATA_OUT => tx1_data_in,
- MED_PACKET_NUM_OUT => open,
+ MED_PACKET_NUM_OUT => tx1_packet_num_in,
MED_READ_IN => tx1_read_out,
-- Internal direction port
INT_DATA_OUT => open,
MED_READ_OUT => rxread2_out,
MED_DATAREADY_OUT => open,
MED_DATA_OUT => open,
- MED_PACKET_NUM_OUT => open,
+ MED_PACKET_NUM_OUT => tx2_packet_num_in,
MED_READ_IN => '1',
-- Internal direction port
INT_DATA_OUT(15 downto 0) => rxdata2,
signal lfsr_c: std_logic_vector (7 downto 0);
begin
CRC_OUT <= lfsr_q;
- CRC_match <= not and_all(lfsr_q);
+ CRC_match <= not or_all(lfsr_c);
lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6);
lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7);
lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5);
- process (CLK,RESET) begin
- if (RESET = '1') then
- lfsr_q <= b"00000000";
- elsif rising_edge(CLK) then
- if (CLK_EN = '1') then
+ process (CLK) begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ lfsr_q <= b"00000000";
+ elsif (CLK_EN = '1') then
lfsr_q <= lfsr_c;
end if;
end if;
end component;
+ component trb_net_CRC8 is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(7 downto 0);
+ CRC_OUT : out std_logic_vector(7 downto 0);
+ CRC_match : out std_logic
+ );
+ end component;
component ddr_off is
port (
RESET_IN : in std_logic;
TX_DATA_IN : in std_logic_vector(15 downto 0);
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
TX_WRITE_IN : in std_logic;
TX_READ_OUT : out std_logic;
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