new dma handler

diff --git a/pexor/kernel-module/pexor_trb.c b/pexor/kernel-module/pexor_trb.c
index 0e2b65a3d046babebc1f455989f2c9552fbff4a5..5d8f74752b2fb4c2a5d608f65c3532b343014727 100644 (file)
--- a/pexor/kernel-module/pexor_trb.c
+++ b/pexor/kernel-module/pexor_trb.c
@@ -75,7 +75,7 @@ struct dev_pexor
 };
 
 #define DMA_BUFFER_NUM_PAGES ((8 * 1024 * 1024) / PAGE_SIZE)
-#define PEXOR_DMA_MAXPOLLS 10000
+#define PEXOR_DMA_MAXPOLLS 1000000
 #define PEXOR_DMA_POLLDELAY 0
 #define PEXOR_MEMWRITE_SIZE 128
 
@@ -1361,23 +1361,35 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg)
       for (loops = 0; loops < PEXOR_DMA_MAXPOLLS * 100; loops++) {
         dmastat = ioread32(priv->pexor.dma_control_stat);
         mb();
-        if (((dmastat & PEXOR_DMA_ENABLED_BIT) == 0) && (dmastat != 0)) {
+        if ((dmastat & PEXOR_TRB_BIT_DMA_FINISHED) != 0) {
+          /* DMA is completed */
+          dmaSize = dmastat >> 8;
           break;
         }
-        if ((dmastat & PEXOR_TRB_BIT_DMA_MORE) != 0)
+        if ((dmastat & PEXOR_TRB_BIT_DMA_MORE) != 0) {
+          /* Card needs more DMA-Buffers */
           break;
+        }
+        if ((dmastat & PEXOR_TRB_BIT_DMA_TIMEOUT) != 0) {
+          /* TRBNet Timeout */
+          pexor_msg(KERN_ERR
+                    "ERROR> wait_dma_complete: TRBNet Timeout Bit set "
+                    "Status: 0x%08x\n",
+                    (unsigned int)dmastat);
+          status = -EFAULT;
+          goto OUT_DMA;
+        }
       }
-      if (loops == PEXOR_DMA_MAXPOLLS * 100) {
+      /* Check for kernel timeout */
+      if (loops == PEXOR_DMA_MAXPOLLS) {
         pexor_msg(KERN_ERR
                   "ERROR> wait_dma_complete: polling longer than %d cycles "
-                  "(delay %d ns) for dma complete! Status: 0x%x\n",
+                  "(delay %d ns) for dma complete! Status: 0x%08x\n",
                   PEXOR_DMA_MAXPOLLS, PEXOR_DMA_POLLDELAY,
                   (unsigned int)dmastat);
-        /* reset DMA */
-        iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
         /* do we need to flush the fifo-buffer? */
         status = -EFAULT;
-        goto OUT_IOCTL;
+        goto OUT_DMA;
       }
 
       /* sync current sg-entry to CPU */
@@ -1387,25 +1399,24 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg)
                               DMA_FROM_DEVICE);
       mb();
       
-      /* check status: do we need another dma for data */
-      if ((dmastat & PEXOR_DMA_ENABLED_BIT) == 0) {
-        dmaSize = dmastat >> 8; //was +=
+      /* Check status: do we need another dma for data */
+      if (dmaSize > 0) {
+        /* No, end DMA */
         break;
       }
       if ((sg_ctr + 1) >= priv->dma.nr_sglist) {
         pexor_msg(KERN_ERR
                   "ERROR> no more DMA buffers available, aborting DMA\n");
-        /* reset DMA */
-        iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
         /* do we need to flush the fifo-buffer? */
         status = -EFAULT;
-        goto OUT_IOCTL;
+        goto OUT_DMA;
       }
     }
 
     status = dmaSize;
-
-#ifdef PEXOR_TRB_DEBUG
+    pexor_msg(KERN_ERR "DMA: dmaSize: %d\n", dmaSize);
+    //#ifdef PEXOR_TRB_DEBUG
+#if 1
     {
       int i;
       pexor_msg(KERN_ERR "DMA: dmaSize: %d\n", dmaSize);
@@ -1418,6 +1429,10 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata *priv, unsigned long arg)
       }
     }
 #endif
+  OUT_DMA:
+    /* reset DMA */
+    iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
+    
   } else {
     /* do FIFO transfer to DMA Buffer */
     pexor_dbg(KERN_ERR "Start FIFO copy to DMA buffer\n");

diff --git a/pexor/kernel-module/pexor_trb.h b/pexor/kernel-module/pexor_trb.h
index 2f37138af325799623b049a54e1c3aa671cc119d..e58e930f2693cc4b817172d0ad719f3f9babd223 100644 (file)
--- a/pexor/kernel-module/pexor_trb.h
+++ b/pexor/kernel-module/pexor_trb.h
@@ -10,9 +10,13 @@
 
 #define PEXOR_BURST                      0x80
 #define PEXOR_DMA_ENABLED_BIT            0x01
+#define PEXOR_TRB_DMA_RESET              0x02
+
+/* DMA Status Register */
 #define PEXOR_TRB_BIT_DMA_ACTIVE         0x01
 #define PEXOR_TRB_BIT_DMA_MORE           0x02
-#define PEXOR_TRB_DMA_RESET              0x02
+#define PEXOR_TRB_BIT_DMA_FINISHED       0x04
+#define PEXOR_TRB_BIT_DMA_TIMEOUT        0x08
 
 #define PEXOR_DRAM                       0x100000       /* TODO: specify meaningful RAM position for fops io functions? */