*** empty log message ***

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index b810473f9aa9ee27744975074c6df29e10919a71..b4683db0d84e5990c12e3ac07d6f3f1b94e55e85 100644 (file)
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -89,24 +89,30 @@ signal fifo_almostfull       : std_logic;
 signal debug_x               : std_logic_vector(7 downto 0);\r
 \r
 attribute syn_preserve : boolean;\r
+attribute syn_noprune  : boolean;\r
 attribute syn_keep     : boolean;\r
+attribute syn_preserve of fifo_wcnt       : signal is true;\r
+attribute syn_keep of fifo_wcnt           : signal is true;\r
+attribute syn_noprune of fifo_wcnt        : signal is true;\r
+attribute syn_preserve of bsm             : signal is true;\r
+attribute syn_keep of bsm                 : signal is true;\r
+attribute syn_noprune of bsm              : signal is true;\r
+\r
+\r
 attribute syn_preserve of syn_data        : signal is true;\r
 attribute syn_keep of syn_data            : signal is true;\r
 attribute syn_preserve of syn_dataready   : signal is true;\r
 attribute syn_keep of syn_dataready       : signal is true;\r
 \r
-attribute syn_preserve of fifo_wcnt       : signal is true; \r
-attribute syn_keep of fifo_wcnt           : signal is true; \r
-attribute syn_preserve of bsm             : signal is true; \r
-attribute syn_keep of bsm                 : signal is true; \r
-\r
 attribute syn_hier : string;\r
 attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";\r
 \r
+\r
 --attribute syn_noprune : boolean;\r
 --attribute syn_noprune of THE_DBG_REG : label is true;\r
 --signal my_debug                 : std_logic_vector(26 downto 0);\r
 \r
+\r
 begin\r
 \r
 \r
@@ -242,7 +248,8 @@ begin
                                                else\r
                                                        NEXT_STATE      <= RD4;\r
                                                end if;\r
-               when RD5    =>  syn_dataready_x <= '1'; \r
+               when RD5    => \r
+                                               syn_dataready_x <= '1';\r
                                                if   ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
                                                        NEXT_STATE      <= WR5;\r
                                                        fifo_rd_en_x    <= '1';\r
@@ -251,15 +258,20 @@ begin
                                                else\r
                                                        NEXT_STATE      <= RD5;\r
                                                end if;\r
-               when WR5    =>  if( (SYN_READ_IN = '1') and (p_really_x = '1') ) then\r
+               when WR5    =>\r
+            if SYN_READ_IN = '0' and syn_dataready = '1' then\r
+                                                       NEXT_STATE      <= WR5;\r
+              syn_dataready_x <= '1';\r
+            elsif ( (SYN_READ_IN = '1') and (p_really_x = '1')  ) then\r
                                                        NEXT_STATE      <= RD2;\r
                                                        fifo_rd_en_x    <= '1';\r
-                                                       --syn_dataready_x <= '1';\r
-                                                       syn_dataready_x <= COMB_DATAREADY_IN;\r
+              syn_dataready_x <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= WR5;\r
+              syn_dataready_x <= p_really_x;\r
                                                end if;\r
-               when WT5    =>  if( SYN_READ_IN = '1' ) then\r
+               when WT5    =>  \r
+                                               if( SYN_READ_IN = '1' ) then\r
                                                        NEXT_STATE <= IDLE;\r
                                                else\r
                                                        NEXT_STATE <= WT5;\r
@@ -299,7 +311,7 @@ end process THE_SYNC_PROC;
 -- DEBUG\r
 ---------------------------------------------------------------------\r
 debug_x(7 downto 4)  <= x"0";\r
-debug_x(3)           <= '0';\r
+debug_x(3)           <= COMB_DATAREADY_IN;\r
 debug_x(2)           <= fifo_rd_en_x;\r
 debug_x(1)           <= p_avail_x;\r
 debug_x(0)           <= p_wait_x;\r