*** empty log message ***

diff --git a/pinout/mdc_oep3.lpf b/pinout/mdc_oep3.lpf
index ee10ef8e6dd397385291a7b061333a981c46f602..ee531444faea19323e29f39feea6d9560153e8d8 100644 (file)
--- a/pinout/mdc_oep3.lpf
+++ b/pinout/mdc_oep3.lpf
@@ -67,12 +67,14 @@ IOBUF  PORT  "COM_STOP_P" IO_TYPE=LVDS25;
   LOCATE COMP  "CS_2"        SITE "F11";
 
 #################################################################
-#Misc TTL Ports
-#################################################################
-#  LOCATE COMP  "TCK"        SITE "L6";
-#  LOCATE COMP  "TMS"        SITE "N5";
-#  LOCATE COMP  "TDZ"        SITE "M6";
-#  LOCATE COMP  "TDA"        SITE "M5";
+#JTAG to CPLD
+#################################################################
+#  LOCATE COMP  "JTAG_TCK"        SITE "L6";
+#  LOCATE COMP  "JTAG_TMS"        SITE "N5";
+#  LOCATE COMP  "JTAG_TDO"        SITE "M6";
+#  LOCATE COMP  "JTAG_TDI"        SITE "M5";
+#  DEFINE PORT GROUP "jtag_grp" "JTAG*" ;
+#  IOBUF GROUP "jtag_grp" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
 
 #################################################################
 #Optical Link Status

diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd
index 695cfa4fd82982d9b60edd3f2efdf24a438ee77d..c318db2ac5769841b36d5860b64d76c79b8e00d9 100644 (file)
--- a/special/handler_lvl1.vhd
+++ b/special/handler_lvl1.vhd
@@ -145,7 +145,7 @@ signal tmg_edge_ctr         : unsigned(15 downto 0);
 signal tmg_edge_found_i     : std_logic;
 signal sr0                  : std_logic;
 signal tmg_edge_async       : std_logic;
-
+signal buf_STATUS_OUT       : std_logic_vector(63 downto 0);
 
 begin
 
@@ -603,29 +603,31 @@ end process THE_MEASURED_DELAY_PROC;
 STAT_PROC : process(CLOCK)
 begin
   if rising_edge(CLOCK) then
-    STATUS_OUT(63 downto 48)  <= std_logic_vector(trigger_length);
-    STATUS_OUT(47 downto 32)  <= std_logic_vector(trigger_edge_count);
-    STATUS_OUT(31 downto 16)  <= lvl1_delay;
-    STATUS_OUT(15)            <= timing_trg_found;
-    STATUS_OUT(14)            <= data_valid;
-    STATUS_OUT(12)            <= not trg_num_match;
-    STATUS_OUT(11)            <= timeout_found;
-    STATUS_OUT(10 downto 8)   <= (others => '0');
-    STATUS_OUT(3 downto 0)    <= bsm_x;
+    buf_STATUS_OUT(63 downto 48)  <= std_logic_vector(trigger_length);
+    buf_STATUS_OUT(47 downto 32)  <= std_logic_vector(trigger_edge_count);
+    buf_STATUS_OUT(31 downto 16)  <= lvl1_delay;
+    buf_STATUS_OUT(15)            <= timing_trg_found;
+    buf_STATUS_OUT(14)            <= data_valid;
+    buf_STATUS_OUT(12)            <= not trg_num_match;
+    buf_STATUS_OUT(11)            <= timeout_found;
+    buf_STATUS_OUT(10 downto 8)   <= (others => '0');
+    buf_STATUS_OUT(3 downto 0)    <= bsm_x;
 
     if (RESET = '1') or (RESET_FLAGS_IN = '1') then
-      STATUS_OUT(7 downto 4) <= (others => '0');
-      STATUS_OUT(13) <= '0';
+      buf_STATUS_OUT(7 downto 4) <= (others => '0');
+      buf_STATUS_OUT(13) <= '0';
     elsif (val_trg = '1') or (invalid_trg = '1') then
-      STATUS_OUT(13)            <= mult_trg_found;
-      STATUS_OUT(7)             <= wrong_polarity;
-      STATUS_OUT(6)             <= spurious_trg;
-      STATUS_OUT(5)             <= missing_tmg;
-      STATUS_OUT(4)             <= short_tmg_trg;
+      buf_STATUS_OUT(13)            <= buf_STATUS_OUT(13) or mult_trg_found;
+      buf_STATUS_OUT(7)             <= buf_STATUS_OUT(7) or wrong_polarity;
+      buf_STATUS_OUT(6)             <= buf_STATUS_OUT(6) or spurious_trg;
+      buf_STATUS_OUT(5)             <= buf_STATUS_OUT(5) or missing_tmg;
+      buf_STATUS_OUT(4)             <= buf_STATUS_OUT(4) or short_tmg_trg;
     end if;
   end if;
 end process STAT_PROC;
 
+STATUS_OUT <= buf_STATUS_OUT;
+
 -- STATISTICS COUNTERS
 -- gk 29.09.10
 STAT_CTR_PROC : process(CLOCK)

diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd
index 537df7d8901f78b7e5870fa56e019e925c336ba5..de694316cea5d6ae4f457184154dceaeb2681bd8 100644 (file)
--- a/special/trb_net_bridge_pcie_endpoint_hub.vhd
+++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd
@@ -244,6 +244,7 @@ begin
       MII_IS_UPLINK              => (NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, 0 => c_YES, others => c_NO), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
       MII_IS_DOWNLINK            => (others => c_YES), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
       MII_IS_UPLINK_ONLY         => (others => c_NO), --NUM_LINKS => c_YES,
+      INIT_UNIQUE_ID             => x"1111222233334444",
       INIT_ENDPOINT_ID           => x"0001",
       INT_NUMBER                 => 3,
       INT_CHANNELS               => (0=>0,1=>1,2=>3,others=>0)

diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd
index 7928776d4c26fc7e9c59ebfdfbae16427e17eccd..b7a71c62db3fb1e0e342bc5c5c1b1d94fde3ba73 100644 (file)
--- a/trb_net16_endpoint_hades_full_handler.vhd
+++ b/trb_net16_endpoint_hades_full_handler.vhd
@@ -624,13 +624,18 @@ begin
 
   process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)
     begin
-      common_stat_reg_i(47 downto 0) <= REGIO_COMMON_STAT_REG_IN(47 downto 0);
+      common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0);
+      common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12);
       common_stat_reg_i(6)       <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6);
-      common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);
-      common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);
-      common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11);
-      if common_ctrl_reg_i(4) = '1' then 
-        common_stat_reg_i(11 downto 9) <= "000";
+
+      if rising_edge(CLK) then
+        if common_ctrl_reg_i(4) = '1' then 
+          common_stat_reg_i(11 downto 9) <= "000";
+        else 
+          common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);
+          common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);
+          common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11);      
+        end if;
       end if;
       common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64);
     end process;

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 43cfc5401ef8d8f78ee2f106b797dfd5f4662839..c444da71a0aa90b77a2d72c07b104ea291985061 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -99,6 +99,7 @@ entity trb_net16_hub_base is
     REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector(15 downto 0) := (others => '0');
     TIMER_TICKS_OUT              : out std_logic_vector(1 downto 0);
     HUB_LED_OUT                  : out std_logic_vector (MII_NUMBER-1 downto 0);
+    UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
     --Fixed status and control ports
     HUB_STAT_CHANNEL             : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
     HUB_STAT_GEN                 : out std_logic_vector (31 downto 0);
@@ -1270,6 +1271,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
         ADDR_OUT => ONEWIRE_ADDR,
         WRITE_OUT=> ONEWIRE_WRITE,
         TEMP_OUT => TEMP_OUT,
+        ID_OUT   => UNIQUE_ID_OUT,
         STAT     => open
         );
   end generate;
@@ -1287,6 +1289,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
         ADDR_OUT => ONEWIRE_ADDR,
         WRITE_OUT=> ONEWIRE_WRITE,
         TEMP_OUT => TEMP_OUT,
+        ID_OUT   => UNIQUE_ID_OUT,
         STAT     => open
         );
   end generate;

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index fc31ee6825981c6f78c389d6a4b4825ad868c607..3bc99b1c5a674598b5feb40ad80822fc982ec01e 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -172,6 +172,7 @@ package trb_net16_hub_func is
     COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0);  --Status of common STAT regs
     MY_ADDRESS_OUT   : out std_logic_vector (15 downto 0);
     HUB_LED_OUT      : out std_logic_vector (MII_NUMBER-1 downto 0);
+    UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
     --Fixed status and control ports
     HUB_STAT_CHANNEL      : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
     HUB_STAT_GEN          : out std_logic_vector (31 downto 0);
@@ -655,6 +656,7 @@ component trb_net16_hub_streaming_port_sctrl is
     ONEWIRE_MONITOR_IN           : in  std_logic;
     ONEWIRE_MONITOR_OUT          : out std_logic;
     MY_ADDRESS_OUT               : out std_logic_vector(15 downto 0);
+    UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
 
     --REGIO INTERFACE
     REGIO_ADDR_OUT               : out std_logic_vector(16-1 downto 0);

diff --git a/trb_net16_hub_streaming_port_sctrl.vhd b/trb_net16_hub_streaming_port_sctrl.vhd
index 052a689fa58e98ac2ab9004ec7cbab6ee3d5bc45..eac5703eeb12578ac9867230eb15a4bf07c7296c 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl.vhd
+++ b/trb_net16_hub_streaming_port_sctrl.vhd
@@ -96,6 +96,7 @@ entity trb_net16_hub_streaming_port_sctrl is
     ONEWIRE_MONITOR_IN           : in  std_logic;
     ONEWIRE_MONITOR_OUT          : out std_logic;
     MY_ADDRESS_OUT               : out std_logic_vector(15 downto 0);
+    UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
 
     --REGIO INTERFACE
     REGIO_ADDR_OUT               : out std_logic_vector(16-1 downto 0);
@@ -312,6 +313,7 @@ begin
       ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
       ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT,
       MY_ADDRESS_OUT     => my_address,
+      UNIQUE_ID_OUT      => UNIQUE_ID_OUT,
       COMMON_CTRL_REGS   => common_ctrl,
       COMMON_STAT_REGS   => common_stat,
       MPLEX_CTRL         => (others => '0'),

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 747727091e9de0af50cc1745eafa7e9930bd0b6c..3d50a50336c3a43211bdd25b7170705723b40c52 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -2130,6 +2130,7 @@ end component;
       ADDR_OUT : out std_logic_vector(2 downto 0);\r
       WRITE_OUT: out std_logic;\r
       TEMP_OUT : out std_logic_vector(11 downto 0);\r
+      ID_OUT   : out std_logic_vector(63 downto 0);\r
       STAT     : out std_logic_vector(31 downto 0)\r
       );\r
   end component;\r
@@ -2149,6 +2150,7 @@ end component;
       ADDR_OUT : out std_logic_vector(2 downto 0);\r
       WRITE_OUT: out std_logic;\r
       TEMP_OUT : out std_logic_vector(11 downto 0);\r
+      ID_OUT   : out std_logic_vector(63 downto 0);\r
       STAT     : out std_logic_vector(31 downto 0)\r
       );\r
   end component;\r

diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
index 40c79af3fa5e796f4e24c943145160fea44fc951..e6b3dcabd7e01c7eb02a1fae8fbce435bd3007b5 100644 (file)
--- a/trb_net_onewire.vhd
+++ b/trb_net_onewire.vhd
@@ -25,6 +25,7 @@ entity trb_net_onewire is
     ADDR_OUT : out std_logic_vector(2 downto 0);
     WRITE_OUT: out std_logic;
     TEMP_OUT : out std_logic_vector(11 downto 0);
+    ID_OUT   : out std_logic_vector(63 downto 0);
     STAT     : out std_logic_vector(31 downto 0)
     );
 end entity;
@@ -367,6 +368,19 @@ begin
 
   TEMP_OUT <= buf_TEMP_OUT;
 
+  PROC_STORE_ID : process begin
+    wait until rising_edge(CLK);
+    if ram_wr = '1' then
+      case ram_addr is
+        when "000" => ID_OUT(15 downto  0) <= word;
+        when "001" => ID_OUT(31 downto 16) <= word;
+        when "010" => ID_OUT(47 downto 32) <= word;
+        when "011" => ID_OUT(63 downto 48) <= word;
+      end case;
+    end if;
+  end process;
+
+
   STAT(0) <= '0';
   STAT(1) <= '0' when input = '0' else '1';
   STAT(2) <= output;

diff --git a/trb_net_onewire_listener.vhd b/trb_net_onewire_listener.vhd
index f722d57ad546f8ec9853d0ac962b7111f6586e65..88b6a1c27c4197c1a730a04d3fb0be64d27d2f1d 100644 (file)
--- a/trb_net_onewire_listener.vhd
+++ b/trb_net_onewire_listener.vhd
@@ -16,6 +16,7 @@ entity trb_net_onewire_listener is
     ADDR_OUT : out std_logic_vector(2 downto 0);
     WRITE_OUT: out std_logic;
     TEMP_OUT : out std_logic_vector(11 downto 0);
+    ID_OUT   : out std_logic_vector(63 downto 0);
     STAT     : out std_logic_vector(31 downto 0)
     );
 end entity;
@@ -241,6 +242,18 @@ begin
   TEMP_OUT  <= buf_TEMP_OUT;
 
 
+  PROC_STORE_ID : process begin
+    wait until rising_edge(CLK);
+    if buf_WRITE_OUT = '1' then
+      case buf_ADDR_OUT is
+        when "000" => ID_OUT(15 downto  0) <= buf_DATA_OUT;
+        when "001" => ID_OUT(31 downto 16) <= buf_DATA_OUT;
+        when "010" => ID_OUT(47 downto 32) <= buf_DATA_OUT;
+        when "011" => ID_OUT(63 downto 48) <= buf_DATA_OUT;
+      end case;
+    end if;
+  end process;
+
   state_bits <= "0000" when state = WAIT_FOR_RESET else
                 "0001" when state = RESETTING else
                 "0010" when state = WAIT_AFTER_RESET else