SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END component;
COMB_DATA_IN => next_INT_INIT_DATA_OUT,
SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
SYN_DATA_OUT => INT_INIT_DATA_OUT,
- SYN_READ_IN => INT_INIT_READ_IN,
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => INT_INIT_READ_IN
);
sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle
SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END component;
COMB_DATA_IN => tmp_INT_DATA_OUT,
SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
SYN_DATA_OUT => INT_DATA_OUT,
- SYN_READ_IN => INT_READ_IN,
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => INT_READ_IN
);
sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
entity trb_net_io_multiplexer is
- generic (BUS_WIDTH : integer := 56;
- MULT_WIDTH : integer := 5);
-
+-- generic (BUS_WIDTH : integer := 56;
+-- MULT_WIDTH : integer := 5);
+ generic (BUS_WIDTH : integer := 52;
+ MULT_WIDTH : integer := 1);
+
port(
-- Misc
CLK : in std_logic;
SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END component;
COMB_DATA_IN => MED_DATA_IN (BUS_WIDTH-MULT_WIDTH-1 downto 0),
SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i),
SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH-MULT_WIDTH)*(i+1)-1 downto (BUS_WIDTH-MULT_WIDTH)*(i)),
- SYN_READ_IN => INT_READ_IN(i),
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => INT_READ_IN(i)
);
end generate;
COMB_DATA_IN => current_mux_buffer,
SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
SYN_DATA_OUT => MED_DATA_OUT,
- SYN_READ_IN => MED_READ_IN,
--- STAT_BUFFER =>
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => MED_READ_IN
);
process (tmp_INT_READ_OUT, INT_DATA_IN)
--Entity decalaration for clock generator
entity trb_net_iobuf is
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ generic (
+-- INIT_DEPTH : integer := 0;
+ INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
+ REPLY_DEPTH : integer := 3); -- or the replyibuf
port(
-- Misc
--Entity decalaration for clock generator
entity trb_net_obuf is
-
+ generic (
+ DATA_COUNT_WIDTH : integer := 4);
port(
-- Misc
SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END component;
signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC;
signal sent_ACK, sent_EOB, sent_DATA : STD_LOGIC;
- signal CURRENT_DATA_COUNT, next_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
- signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (15 downto 0);
+ signal CURRENT_DATA_COUNT, next_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
+-- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
+ signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
signal TRANSMITTED_BUFFERS, next_TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0);
signal increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS : STD_LOGIC;
COMB_DATA_IN => current_output_buffer,
SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
SYN_DATA_OUT => MED_DATA_OUT,
- SYN_READ_IN => MED_READ_IN,
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => MED_READ_IN
);
decrease_TRANSMITTED_BUFFERS <= GOT_ACK_IN;
INT_DATAREADY_IN, INT_DATA_IN, sent_ACK, sent_EOB,
current_ACK_word,current_EOB_word, sbuf_free, sent_data,
max_DATA_COUNT_minus_one,next_DATA_COUNT,
- max_DATA_COUNT,
next_TRANSMITTED_BUFFERS)
begin
current_output_buffer <= current_NOP_word;
end if;
--finally, block data read if the rec buffer is full
if sent_data = '0' or
- (next_DATA_COUNT = max_DATA_COUNT_minus_one) or
+ (next_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0)) or
next_TRANSMITTED_BUFFERS(1) = '1'
then
next_INT_READ_OUT <= '0';
current_EOB_word(TYPE_POSITION) <= TYPE_EOB;
current_EOB_word(47 downto 0) <= (others => '0');
- gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT)
+ gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT_minus_one)
begin
if (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) then
sent_EOB <= '1';
sent_DATA <= not TRANSMITTED_BUFFERS(1);
-- generate max_DATA_COUNT, comb. operation which should be registered
- next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else
- "0000000000001000" when REC_BUFFER_SIZE_IN="0010" else
- "0000000000010000" when REC_BUFFER_SIZE_IN="0011" else
- "0000000000100000" when REC_BUFFER_SIZE_IN="0100" else
- "0000000000000010";
+-- next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else
+-- "0000000000001000" when REC_BUFFER_SIZE_IN="0010" else
+-- "0000000000010000" when REC_BUFFER_SIZE_IN="0011" else
+-- "0000000000100000" when REC_BUFFER_SIZE_IN="0100" else
+-- "0000000000000010";
next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else
"0000000000000111" when REC_BUFFER_SIZE_IN="0010" else
"0000000000001111" when REC_BUFFER_SIZE_IN="0011" else
begin
if rising_edge(CLK) then
if RESET = '1' then
- max_DATA_COUNT <= (1 => '1', others => '0');
+-- max_DATA_COUNT <= (1 => '1', others => '0');
max_DATA_COUNT_minus_one <= (0 => '1', others => '0');
else
- max_DATA_COUNT <= next_max_DATA_COUNT;
+-- max_DATA_COUNT <= next_max_DATA_COUNT;
max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one;
end if;
end if;
entity trb_net_priority_arbiter is
- generic (WIDTH : integer := 16);
+-- generic (WIDTH : integer := 16);
+ generic (WIDTH : integer := 2);
port(
-- Misc
-------------------------------------------------------------------------------
-- Single buffer with one more buffer to keep the speed of the datalink
-- The sbuf can be connected to a combinatorial logic (as an output buffer)
--- to provide the synchronous logic
+-- to provide the synchronous logic
+--
+-- 2 versions are provided
+-- VERSION=0 is the fast version, so double buffering is done
+-- VERSION=1 is half data rate: After data has beed written to the sbuf,
+-- the input read signal is stalled until the buffer is empty.
+-- Maybe enough for trigger and slow control channels
-------------------------------------------------------------------------------
entity trb_net_sbuf is
- generic (DATA_WIDTH : integer := 56);
+ generic (DATA_WIDTH : integer := 56;
+ VERSION: integer := 1);
-- generic (DATA_WIDTH : integer := 1);
-
+
port(
-- Misc
CLK : in std_logic;
SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END trb_net_sbuf;
signal current_got_overflow, next_got_overflow : std_logic;
signal combined_COMB_DATAREADY_IN: std_logic;
+ signal use_current_b1_buffer: std_logic;
+
begin
COMB_next_READ_OUT <= current_next_READ_OUT;
SYN_DATA_OUT <= current_b2_buffer;
SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
- STAT_BUFFER(0) <= current_got_overflow;
- STAT_BUFFER(31 downto 1) <= (others => '0');
+ STAT_BUFFER <= current_got_overflow;
combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN);
+
+ GEN1: if VERSION = 0 generate
+ MUX: process (use_current_b1_buffer)
+ begin -- simple MUX
+ if use_current_b1_buffer = '1' then
+ next_b2_buffer <= current_b1_buffer;
+ else
+ next_b2_buffer <= COMB_DATA_IN;
+ end if;
+ end process;
+ end generate;
+ GEN2: if VERSION = 1 generate
+ next_b2_buffer <= COMB_DATA_IN;
+ end generate;
+
COMB: process (current_buffer_state, COMB_DATAREADY_IN, COMB_READ_IN,
SYN_READ_IN, COMB_DATA_IN, current_b1_buffer, current_b2_buffer,
current_SYN_DATAREADY_OUT, current_got_overflow)
begin -- process COMB
next_buffer_state <= current_buffer_state;
next_next_READ_OUT <= '1';
--- next_b2_buffer <= current_b2_buffer;
--- next_b1_buffer <= current_b1_buffer;
- next_b1_buffer <= COMB_DATA_IN;
- next_b2_buffer <= COMB_DATA_IN;
- move_b1_buffer <= '0';
+ if VERSION = 0 then
+ next_b1_buffer <= COMB_DATA_IN;
+ move_b1_buffer <= '0';
+ end if;
+ use_current_b1_buffer <= '0'; --by default COMB_DATA_IN;
move_b2_buffer <= '0';
next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
next_got_overflow <= current_got_overflow;
if current_buffer_state = BUFFER_EMPTY then
-
if combined_COMB_DATAREADY_IN = '1' then
-- COMB logic is writing into the sbuf
next_buffer_state <= BUFFER_B2_FULL;
- next_next_READ_OUT <= '0';
--- next_b2_buffer <= COMB_DATA_IN;
+ if VERSION = 1 then
+ next_next_READ_OUT <= '0';
+ end if;
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
end if;
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
next_buffer_state <= BUFFER_B2_FULL;
- next_next_READ_OUT <= '0';
--- next_b2_buffer <= COMB_DATA_IN;
+ if VERSION = 1 then
+ next_next_READ_OUT <= '0';
+ end if;
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
elsif combined_COMB_DATAREADY_IN = '1' then
-- buffer
next_buffer_state <= BUFFER_B1_FULL;
next_next_READ_OUT <= '0'; --PLEASE stop writing
--- next_b1_buffer <= COMB_DATA_IN;
move_b1_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
elsif SYN_READ_IN = '1' then
-- at the same time syn port is reading
next_buffer_state <= BUFFER_B1_FULL;
next_next_READ_OUT <= '0';
--- next_b1_buffer <= COMB_DATA_IN;
- next_b2_buffer <= current_b1_buffer;
+ use_current_b1_buffer <= '1';
move_b1_buffer <= '1';
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
elsif SYN_READ_IN = '1' then
next_buffer_state <= BUFFER_B2_FULL;
next_next_READ_OUT <= '0';
--- next_b2_buffer <= current_b1_buffer;
next_SYN_DATAREADY_OUT <= '1';
else
next_buffer_state <= BUFFER_B1_FULL;
end if;
end if;
end process;
-
+
+ GEN6: if VERSION = 0 generate
REG2 : process(CLK)
begin
if rising_edge(CLK) then
current_b1_buffer <= current_b1_buffer;
end if;
end if;
-end process;
+ end process;
+ end generate;
+
+
REG3 : process(CLK)
begin
if rising_edge(CLK) then
);
END trb_net_term_ibuf;
-architecture trb_net_term_ibuf_arch of trb_term_net_ibuf is
+architecture trb_net_term_ibuf_arch of trb_net_term_ibuf is
component trb_net_sbuf is
SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
SYN_READ_IN: in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ STAT_BUFFER: out STD_LOGIC
);
END component;
COMB_DATA_IN => tmp_INT_DATA_OUT,
SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
SYN_DATA_OUT => INT_DATA_OUT,
- SYN_READ_IN => INT_READ_IN,
- CTRL_BUFFER => (others => '0')
+ SYN_READ_IN => INT_READ_IN
);
sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
if RESET = '1' then
is_locked <= '0';
reg_eob_out <= '0';
- current_last_header <= (others => '0');
elsif CLK_EN = '1' then
if release_locked = '1' then
is_locked <= '0';
is_locked <= got_locked;
end if;
reg_eob_out <= got_eob_out;
- current_last_header <= next_last_header;
else
is_locked <= is_locked;
reg_eob_out <= reg_eob_out;
- current_last_header <= current_last_header;
end if;
end if;
end process;
jspc29 / trbnet.git / commitdiff