update to included features list

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index cc5bd999bb3f14943d6113d8e5ab108730a3ec37..8276394a96cd426b633c83c730e4038b024a3632 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -6,9 +6,10 @@
 \hline\hline
 1 & \multicolumn{3}{X|}{``Central'' - For a normal central FPGA design with Cts and/or GbE}\\
  & 3 -- 0   & ExtModule   & Type of external trigger module (0: none, 1: CBM MBS, 2: Mainz M2)\\ 
- & 7 -- 4   & CtsTdc      & Number of TDC channels included. Usually connected to the first trigger inputs of the CTS. 
+ & 4        & CtsTdc      & TDC channels included. Usually connected to the first trigger inputs of the CTS. 
 If a trigger module is present, the first channel will connect to its async output signal \\
- & 8        & CtsTdcX     & The connection of TDC channels is non-standard. Refer to documentation. \\
+ & 5        & CtsTdcX     & The connection of TDC channels is non-standard. Refer to documentation. \\
+ & 11 -- 8  & DoubleEdge  & See table 2.\\
  & 15       & CTS         & The design contains a CTS module. A complete list of components can be obtained from the 
 CTS registers. \\
  & 16       & GbeData     & Event data is sent via GbE \\
@@ -16,7 +17,7 @@ CTS registers. \\
  & 19 -- 18 & GbeDataBuf  & Size of the buffer for event data. 1: 64 kB \\
  & 21 -- 20 & GbeCtrlBuf  & Size of the buffer for sctrl data. 1: 4 kB, 2: 64 kB \\
  & 22       & GbeMultBuf  & GbE sctrl data can be split to multiple packets\\
- 
+ & 23       & GbE         & Contains a GbE module \\
  & 26 -- 24 & Sfp         & Number of SFP configured for TrbNet connections\\
  & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
  & 43       & Uart        & Uart on RJ45\_CLOCK(4) (TTL)\\