--- /dev/null
+-- an active api together with an iobuf
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_endpoint_0_trg_1_api is
+
+ generic (
+ API_TYPE : integer range 0 to 1 := 1;
+ INIT_DEPTH : integer range 0 to 6 := 0;
+ REPLY_DEPTH : integer range 0 to 6 := 1;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 1;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 1;
+ SBUF_VERSION : integer range 0 to 1 := 0;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0;
+ DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0;
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic; -- Media is reading
+
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+
+ -- APL Transmitter port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out std_logic_vector(31 downto 0);
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ MPLEX_CTRL: in std_logic_vector (31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_api is
+
+component trb_net16_iobuf is
+
+ generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 3); -- or the replyibuf
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+end component;
+
+component trb_net16_base_api is
+ generic (
+ API_TYPE : integer := 1;
+ FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ SBUF_VERSION : integer range 0 to 1 := 0
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- This is just a clone from trb_net_iobuf
+
+ INT_MASTER_DATAREADY_OUT: out std_logic;
+ INT_MASTER_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN: in std_logic;
+
+ INT_MASTER_DATAREADY_IN: in std_logic;
+ INT_MASTER_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT: out std_logic;
+
+
+ INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the SLAVE path)
+ INT_SLAVE_DATAREADY_OUT: out std_logic;
+ INT_SLAVE_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN: in std_logic;
+
+ INT_SLAVE_DATAREADY_IN: in std_logic;
+ INT_SLAVE_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end component;
+
+
+
+component trb_net16_io_multiplexer is
+
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic;
+
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic;
+
+ -- Internal direction port
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL: in std_logic_vector (31 downto 0);
+ STAT: out std_logic_vector (31 downto 0)
+ );
+end component;
+
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
+
+signal apl_to_buf_INIT_DATAREADY: std_logic;
+signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
+signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+signal apl_to_buf_INIT_READ : std_logic;
+
+signal buf_to_apl_INIT_DATAREADY: std_logic;
+signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0);
+signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+signal buf_to_apl_INIT_READ : std_logic;
+
+signal apl_to_buf_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0);
+signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+signal apl_to_buf_REPLY_READ : std_logic;
+
+signal buf_to_apl_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0);
+signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+signal buf_to_apl_REPLY_READ : std_logic;
+
+-- for the connection to the multiplexer
+signal MED_INIT_DATAREADY_OUT : std_logic;
+signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0);
+signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+signal MED_INIT_READ_IN : std_logic;
+
+signal MED_INIT_DATAREADY_IN : std_logic;
+signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0);
+signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+signal MED_INIT_READ_OUT : std_logic;
+
+signal MED_REPLY_DATAREADY_OUT : std_logic;
+signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0);
+signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+signal MED_REPLY_READ_IN : std_logic;
+
+signal MED_REPLY_DATAREADY_IN : std_logic;
+signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0);
+signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+signal MED_REPLY_READ_OUT : std_logic;
+
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0);
+signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0);
+
+begin
+
+ --Connections for data channel
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
+ gendat: if i = DAT_CHANNEL generate
+ m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT;
+ MED_INIT_READ_IN <= m_READ_IN(i*2);
+ MED_REPLY_READ_IN <= m_READ_IN(i*2+1);
+ MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
+ MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
+ MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
+ MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
+ MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
+ m_READ_OUT(i*2) <= MED_INIT_READ_OUT;
+ m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT;
+ end generate;
+ genelse: if i /= DAT_CHANNEL generate
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
+ end generate;
+ end generate;
+
+
+
+ gen_actapi: if API_TYPE = 1 generate
+ DAT_ACTIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 1,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0,
+ SBUF_VERSION => SBUF_VERSION
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl
+ );
+ end generate;
+
+ gen_pasapi: if API_TYPE = 0 generate
+ DAT_PASSIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 0,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0,
+ SBUF_VERSION => SBUF_VERSION
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_REPLY_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_INIT_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl
+ );
+ end generate;
+api_stat_fifo_to_apl <= buf_api_stat_fifo_to_apl;
+api_stat_fifo_to_int <= buf_api_stat_fifo_to_int;
+
+STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
+STAT_api_control_signals(3) <= APL_WRITE_IN;
+STAT_api_control_signals(4) <= APL_SEND_IN;
+STAT_api_control_signals(7 downto 5) <= (others => '0');
+STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
+STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
+STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
+STAT_api_control_signals(28 downto 13) <= (others => '0');
+
+STAT_api_control_signals(31) <= buf_to_apl_INIT_READ;
+--STAT_api_control_signals(30) <= buf_to_apl_INIT_PACKET_NUM(0);
+--STAT_api_control_signals(29) <= buf_to_apl_INIT_DATAREADY;
+STAT_api_control_signals(30) <= buf_api_stat_fifo_to_apl(3);
+STAT_api_control_signals(29) <= buf_api_stat_fifo_to_apl(14);
+
+
+IOBUF: trb_net16_iobuf
+
+ generic map (INIT_DEPTH => INIT_DEPTH,
+ REPLY_DEPTH => REPLY_DEPTH)
+
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_INIT_READ_IN,
+
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_REPLY_READ_IN,
+
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ,
+
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
+
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
+
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
+
+ -- Status and control port
+ STAT_GEN => STAT_GEN,
+ STAT_LOCKED => STAT_LOCKED,
+ STAT_INIT_BUFFER => buf_STAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_GEN,
+ CTRL_LOCKED => CTRL_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
+ );
+
+STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER;
+
+ MPLEX: trb_net16_io_multiplexer
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT => m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN => m_READ_OUT,
+ INT_DATAREADY_IN => m_DATAREADY_OUT,
+ INT_DATA_IN => m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT => m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
+
+end architecture;
+
--- /dev/null
+-- a trigger receiver - as simple as possible
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_endpoint_1_trg_0_api is
+
+ generic (
+ TRG_INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ TRG_REPLY_DEPTH : integer := 0; -- or the replyibuf
+ MUX_WIDTH : integer := 3;
+ MUX_SECURE_MODE : integer := 0;
+ TRG_CHANNEL : integer := 0;
+ DATA_WIDTH : integer := 16; --not to be changed
+ NUM_WIDTH : integer := 2; --not to be changed
+ TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next
+ -- trigger comes in. if 1 these can be valid on falling edge of hold_trm only
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
+ MED_READ_IN: in std_logic; -- Media is reading
+
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ TRG_GOT_TRIGGER_OUT : out std_logic;
+ TRG_DTYPE_OUT : out std_logic_vector(3 downto 0);
+ TRG_SEQNR_OUT : out std_logic_vector(7 downto 0);
+ TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ TRG_RELEASE_IN : in std_logic;
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_api_control_signals: out std_logic_vector(31 downto 0);
+ STAT_MPLEX: out std_logic_vector(31 downto 0);
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ MPLEX_CTRL: in std_logic_vector (31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_endpoint_1_trg_0_api_arch of trb_net16_endpoint_1_trg_0_api is
+
+ component trb_net16_iobuf is
+ generic (INIT_DEPTH : integer := TRG_INIT_DEPTH; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := TRG_REPLY_DEPTH); -- or the replyibuf
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+ end component;
+ component trb_net16_io_multiplexer is
+ generic (
+ DATA_WIDTH : integer := DATA_WIDTH;
+ NUM_WIDTH : integer := NUM_WIDTH;
+ MUX_WIDTH : integer range 1 to 5 := MUX_WIDTH;
+ MUX_SECURE_MODE : integer range 0 to 1 := MUX_SECURE_MODE --use sbufs or not?
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic;
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic;
+ -- Internal direction port
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ -- Status and control port
+ CTRL: in std_logic_vector (31 downto 0);
+ STAT: out std_logic_vector (31 downto 0)
+ );
+ end component;
+ component trb_net16_term is
+ generic (
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE
+ --if secure_mode is not used, apl must provide error pattern and dtype until
+ --next trigger comes in. In secure mode these must be available when hold_trm goes low
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_DATAREADY_IN: in std_logic;
+ INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_READ_OUT: out std_logic;
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_GOT_TRM: out std_logic;
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
+ -- Status and control port
+ );
+ end component;
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
+
+ signal apl_to_buf_INIT_DATAREADY: std_logic;
+ signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
+ signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+ signal apl_to_buf_INIT_READ : std_logic;
+
+ signal buf_to_apl_INIT_DATAREADY: std_logic;
+ signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0);
+ signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
+ signal buf_to_apl_INIT_READ : std_logic;
+
+ signal apl_to_buf_REPLY_DATAREADY: std_logic;
+ signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0);
+ signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+ signal apl_to_buf_REPLY_READ : std_logic;
+
+ signal buf_to_apl_REPLY_DATAREADY: std_logic;
+ signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0);
+ signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
+ signal buf_to_apl_REPLY_READ : std_logic;
+
+ -- for the connection to the multiplexer
+ signal MED_INIT_DATAREADY_OUT : std_logic;
+ signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0);
+ signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+ signal MED_INIT_READ_IN : std_logic;
+
+ signal MED_INIT_DATAREADY_IN : std_logic;
+ signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0);
+ signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+ signal MED_INIT_READ_OUT : std_logic;
+
+ signal MED_REPLY_DATAREADY_OUT : std_logic;
+ signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0);
+ signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
+ signal MED_REPLY_READ_IN : std_logic;
+
+ signal MED_REPLY_DATAREADY_IN : std_logic;
+ signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0);
+ signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
+ signal MED_REPLY_READ_OUT : std_logic;
+
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*(2**MUX_WIDTH)-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*(2**MUX_WIDTH)-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+begin
+-------------------------------------------------
+--Connection between multiplexer and iobuf
+-------------------------------------------------
+ --Connections for data and trigger channel
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
+ gentrg: if i = TRG_CHANNEL generate
+ m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT;
+ MED_INIT_READ_IN <= m_READ_IN(i*2);
+ MED_REPLY_READ_IN <= m_READ_IN(i*2+1);
+ MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
+ MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
+ MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
+ MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
+ MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
+ m_READ_OUT(i*2) <= MED_INIT_READ_OUT;
+ m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT;
+ end generate;
+ genelse: if i /= TRG_CHANNEL generate
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
+ end generate;
+ end generate;
+
+IOBUF: trb_net16_iobuf
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_INIT_READ_IN,
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_REPLY_READ_IN,
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
+ -- Status and control port
+ STAT_GEN => STAT_GEN,
+ STAT_LOCKED => STAT_LOCKED,
+ STAT_INIT_BUFFER => STAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_GEN,
+ CTRL_LOCKED => CTRL_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
+ );
+
+ MPLEX: trb_net16_io_multiplexer
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET ,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN =>m_READ_OUT,
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT =>m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
+
+
+ TRM_INIT : trb_net16_term
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_REPLY_DATA,
+ INT_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM,
+ INT_READ_IN => apl_to_buf_REPLY_READ,
+ INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
+ INT_DATA_IN => buf_to_apl_INIT_DATA,
+ INT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
+ INT_READ_OUT => buf_to_apl_INIT_READ,
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => TRG_DTYPE_OUT,
+ APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
+ APL_SEQNR_OUT => TRG_SEQNR_OUT,
+ APL_GOT_TRM => TRG_GOT_TRIGGER_OUT,
+ APL_RELEASE_TRM => TRG_RELEASE_IN,
+ APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
+ -- Status and control port
+ );
+
+
+-- TRM_REPLY : trb_net16_term
+-- port map(
+-- -- Misc
+-- CLK => CLK,
+-- RESET => RESET,
+-- CLK_EN => CLK_EN,
+-- INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+-- INT_DATA_OUT => apl_to_buf_INIT_DATA,
+-- INT_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM,
+-- INT_READ_IN => apl_to_buf_INIT_READ,
+-- INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+-- INT_DATA_IN => buf_to_apl_REPLY_DATA,
+-- INT_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM,
+-- INT_READ_OUT => buf_to_apl_REPLY_READ,
+-- -- "mini" APL, just to see the triggers coming in
+-- APL_DTYPE_OUT => open,
+-- APL_ERROR_PATTERN_OUT => open,
+-- APL_SEQNR_OUT => open,
+-- APL_GOT_TRM => open,
+-- APL_RELEASE_TRM => '1',
+-- APL_ERROR_PATTERN_IN => (others => '0')
+-- -- Status and control port
+-- );
+apl_to_buf_INIT_DATAREADY <= '0';
+apl_to_buf_INIT_DATA <= (others => '0');
+apl_to_buf_INIT_PACKET_NUM <= (others => '0');
+buf_to_apl_REPLY_READ <= '1';
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- this is an trigger receiver combined with a passive api
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_endpoint_1_trg_1_api is
+
+ generic (
+ --api type for data channel
+ API_TYPE : integer range 0 to 1 := 0;
+ --Fifo for data channel
+ DAT_INIT_DEPTH : integer range 0 to 7 := 2;
+ DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
+ DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
+ DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
+ --SBUF_DATA_VERSION : integer range 0 to 1 := 0;
+ --Fifo for TRG channel
+ TRG_INIT_DEPTH : integer range 0 to 7 := 0;
+ TRG_REPLY_DEPTH : integer range 0 to 7 := 0;
+ TRG_SECURE_MODE : integer range 0 to 1 := 0;
+ --SBUF_TRG_VERSION : integer range 0 to 1 := 0;
+ --Multiplexer
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0;
+ TRG_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0;
+ DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 2;
+ --General
+ DATA_WIDTH : integer range 16 to 16 := 16;
+ NUM_WIDTH : integer range 2 to 2 := 2
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic; -- Media is reading
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- APL Transceiver port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+
+ -- TRG Receiver port
+ TRG_GOT_TRIGGER_OUT : out std_logic;
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ TRG_DTYPE_OUT : out std_logic_vector(3 downto 0);
+ TRG_SEQNR_OUT : out std_logic_vector(7 downto 0);
+ TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ TRG_RELEASE_IN : in std_logic;
+
+ -- Status and control port => for debugging
+ STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0);
+ CTRL_DAT_GEN: in std_logic_vector (31 downto 0);
+ CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_TRG_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_TRG_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_TRG_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_TRG_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_TRG_api_control_signals: out std_logic_vector(31 downto 0);
+ CTRL_TRG_GEN: in std_logic_vector (31 downto 0);
+ CTRL_TRG_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_TRG_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_TRG_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_MPLEX: out std_logic_vector(31 downto 0);
+ MPLEX_CTRL: in std_logic_vector (31 downto 0);
+ DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_endpoint_1_trg_1_api_arch of trb_net16_endpoint_1_trg_1_api_endpoint is
+
+ component trb_net16_iobuf is
+
+ generic (
+ INIT_DEPTH : integer := 1;
+ REPLY_DEPTH : integer := 1
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_base_api is
+ generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_term is
+ generic (
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ SECURE_MODE : integer range 0 to 1 := 0
+ --if secure_mode is not used, apl must provide error pattern and dtype until
+ --next trigger comes in. In secure mode these must be available when hold_trm goes low
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_DATAREADY_IN: in std_logic;
+ INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_READ_OUT: out std_logic;
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_GOT_TRM: out std_logic;
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
+ -- Status and control port
+ );
+ end component;
+
+ component trb_net16_io_multiplexer is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
+ MED_READ_OUT: out std_logic;
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
+ MED_READ_IN: in std_logic;
+ -- Internal direction port
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ -- Status and control port
+ CTRL: in std_logic_vector (31 downto 0);
+ STAT: out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
+signal apl_to_buf_DAT_INIT_DATAREADY: std_logic;
+signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_INIT_READ : std_logic;
+
+signal buf_to_apl_DAT_INIT_DATAREADY: std_logic;
+signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_INIT_READ : std_logic;
+
+signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_REPLY_READ : std_logic;
+
+signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_REPLY_READ : std_logic;
+
+signal apl_to_buf_TRG_INIT_DATAREADY: std_logic;
+signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_INIT_READ : std_logic;
+
+signal buf_to_apl_TRG_INIT_DATAREADY: std_logic;
+signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_INIT_READ : std_logic;
+
+signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_REPLY_READ : std_logic;
+
+signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_REPLY_READ : std_logic;
+
+-- for the connection to the multiplexer
+signal MED_DAT_INIT_DATAREADY_OUT : std_logic;
+signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_INIT_READ_IN : std_logic;
+
+signal MED_DAT_INIT_DATAREADY_IN : std_logic;
+signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_INIT_READ_OUT : std_logic;
+
+signal MED_DAT_REPLY_DATAREADY_OUT : std_logic;
+signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_READ_IN : std_logic;
+
+signal MED_DAT_REPLY_DATAREADY_IN : std_logic;
+signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_READ_OUT : std_logic;
+
+signal MED_TRG_INIT_DATAREADY_OUT : std_logic;
+signal MED_TRG_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_INIT_READ_IN : std_logic;
+
+signal MED_TRG_INIT_DATAREADY_IN : std_logic;
+signal MED_TRG_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_INIT_READ_OUT : std_logic;
+
+signal MED_TRG_REPLY_DATAREADY_OUT : std_logic;
+signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_READ_IN : std_logic;
+
+signal MED_TRG_REPLY_DATAREADY_IN : std_logic;
+signal MED_TRG_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_READ_OUT : std_logic;
+
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+begin
+
+ --Connections for data and trigger channel
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
+ gendat: if i = DAT_CHANNEL generate
+ m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT;
+ MED_DAT_INIT_READ_IN <= m_READ_IN(i*2);
+ MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1);
+ MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
+ MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
+ MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
+ MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
+ MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
+ m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT;
+ m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT;
+ end generate;
+ gentrg: if i = TRG_CHANNEL generate
+ m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT;
+ MED_TRG_INIT_READ_IN <= m_READ_IN(i*2);
+ MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1);
+ MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
+ MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
+ MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
+ MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
+ MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
+ m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT;
+ m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT;
+ end generate;
+ genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
+ end generate;
+ end generate;
+
+ gen_actapi: if API_TYPE = 1 generate
+ DAT_ACTIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 1,
+ FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
+
+ gen_pasapi: if API_TYPE = 0 generate
+ DAT_PASSIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 0,
+ FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
+
+STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
+STAT_DAT_api_control_signals(3) <= APL_WRITE_IN;
+STAT_DAT_api_control_signals(4) <= APL_SEND_IN;
+STAT_DAT_api_control_signals(7 downto 5) <= (others => '0');
+STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0);
+STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY;
+STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ;
+STAT_DAT_api_control_signals(31 downto 13) <= (others => '0');
+
+
+
+DAT_IOBUF: trb_net16_iobuf
+ generic map(
+ INIT_DEPTH => DAT_INIT_DEPTH,
+ REPLY_DEPTH => DAT_REPLY_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_DAT_INIT_READ_IN,
+ MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+ MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN,
+ MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ,
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ,
+ -- Status and control port
+ STAT_GEN => STAT_DAT_GEN,
+ STAT_LOCKED => STAT_DAT_LOCKED,
+ STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_DAT_GEN,
+ CTRL_LOCKED => CTRL_DAT_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER
+ );
+
+ TRG_IOBUF: trb_net16_iobuf
+ generic map(
+ INIT_DEPTH => TRG_INIT_DEPTH,
+ REPLY_DEPTH => TRG_REPLY_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_TRG_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_TRG_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_TRG_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_TRG_INIT_READ_IN,
+ MED_INIT_DATAREADY_IN => MED_TRG_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_TRG_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_TRG_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_TRG_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+ MED_REPLY_DATAREADY_OUT => MED_TRG_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_TRG_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_TRG_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_TRG_REPLY_READ_IN,
+ MED_REPLY_DATAREADY_IN => MED_TRG_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_TRG_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_TRG_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_TRG_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_TRG_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_TRG_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_TRG_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_TRG_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_TRG_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_TRG_INIT_READ,
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_TRG_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_TRG_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_TRG_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_TRG_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_TRG_REPLY_READ,
+ -- Status and control port
+ STAT_GEN => STAT_TRG_GEN,
+ STAT_LOCKED => STAT_TRG_LOCKED,
+ STAT_INIT_BUFFER => STAT_TRG_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_TRG_REPLY_BUFFER,
+ CTRL_GEN => CTRL_TRG_GEN,
+ CTRL_LOCKED => CTRL_TRG_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_TRG_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_TRG_CTRL_REPLY_BUFFER
+ );
+
+ MPLEX: trb_net16_io_multiplexer
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN =>m_READ_OUT,
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT =>m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
+
+ TRG_INIT : trb_net16_term
+ generic map (
+ FIFO_TERM_BUFFER_DEPTH => 0,
+ SECURE_MODE => TRG_SECURE_MODE
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_TRG_REPLY_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_TRG_REPLY_DATA,
+ INT_PACKET_NUM_OUT => apl_to_buf_TRG_REPLY_PACKET_NUM,
+ INT_READ_IN => apl_to_buf_TRG_REPLY_READ,
+ INT_DATAREADY_IN => buf_to_apl_TRG_INIT_DATAREADY,
+ INT_DATA_IN => buf_to_apl_TRG_INIT_DATA,
+ INT_PACKET_NUM_IN => buf_to_apl_TRG_INIT_PACKET_NUM,
+ INT_READ_OUT => buf_to_apl_TRG_INIT_READ,
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => TRG_DTYPE_OUT,
+ APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
+ APL_SEQNR_OUT => TRG_SEQNR_OUT,
+ APL_GOT_TRM => TRG_GOT_TRIGGER_OUT,
+ APL_RELEASE_TRM => TRG_RELEASE_IN,
+ APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
+ -- Status and control port
+ );
+
+
+
+apl_to_buf_TRG_INIT_DATAREADY <= '0';
+apl_to_buf_TRG_INIT_DATA <= (others => '0');
+apl_to_buf_TRG_INIT_PACKET_NUM <= (others => '0');
+buf_to_apl_TRG_REPLY_READ <= '1';
+end architecture;
--- /dev/null
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.std_logic_ARITH.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+use work.trb_net_std.all;\r
+\r
+\r
+entity trb_net16_hub_base is\r
+ generic{\r
+ --media interfaces\r
+ MII_NUMBER : integer range 2 to 16 := 2;\r
+ MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
+ MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
+ -- settings for apis\r
+ API_NUMBER : integer range 0 to 16 := 1;\r
+ API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3";\r
+ --channel, each api is connected to\r
+ API_TYPE : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+ API_INIT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+ API_REPLY_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+ API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+ API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+ --trigger reading interfaces\r
+ TRG_NUMBER : integer range 0 to 16 := 2;\r
+ TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10";\r
+ --general settings\r
+ MUX_SECURE_MODE : integer range 0 to 1 := 0;\r
+ MUX_WIDTH : integer range 1 to 5 := 3;\r
+ MUX_CTRL_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3;\r
+ DATA_WIDTH : integer range 16 to 16 := 16;\r
+ NUM_WIDTH : integer range 2 to 2 := 2\r
+ }\r
+ port {\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ \r
+ --Media interfacces\r
+ --each port is one bit bigger than actually necessary to avoid error messages\r
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0);\r
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
+ MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0);\r
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media\r
+ MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0);\r
+ --API: interfaces\r
+ APL_DATA_IN : in std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
+ APL_WRITE_IN : in std_logic_vector (APL_NUMBER downto 0);\r
+ APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
+ APL_SHORT_TRANSFER_IN : in std_logic_vector (APL_NUMBER downto 0);\r
+ APL_DTYPE_IN : in std_logic_vector (APL_NUMBER*4 downto 0);\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector (APL_NUMBER*32 downto 0);\r
+ APL_SEND_IN : in std_logic_vector (APL_NUMBER downto 0);\r
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (APL_NUMBER*16 downto 0);\r
+ APL_DATA_OUT : out std_logic_vector (APL_NUMBER*16 downto 0);\r
+ APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
+ APL_TYP_OUT : out std_logic_vector (APL_NUMBER*3 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
+ APL_READ_IN : in std_logic_vector (APL_NUMBER downto 0);\r
+ APL_RUN_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
+ APL_MY_ADDRESS_IN : in std_logic_vector (APL_NUMBRT*16 downto 0);\r
+ APL_SEQNR_OUT : out std_logic_vector (APL_NUMBER*8 downto 0);\r
+ --TRG interfaces\r
+ TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0);\r
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);\r
+ TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0);\r
+ TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0);\r
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0);\r
+ TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0);\r
+ --Status ports (for debugging)\r
+ HUB_CHANNEL_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0);\r
+ HUB_GEN_STAT : out std_logic_vector (31 downto 0);\r
+ MPLEX_CTRL : out std_logic_vector (MII_NUMBER*32-1 downto 0);\r
+ \r
+ }\r
+end entity;\r
+\r
+architecture trb_net16_hub_base_arch of trb_net16_hub_base is\r
+\r
+ signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+ signal m_DATA_OUT : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+ signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+ signal m_READ_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+ signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+ signal m_DATA_IN : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+ signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+ signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+\r
+ signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+ signal hub_to_buf_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+ signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+ signal hub_to_buf_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+ signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+ signal buf_to_hub_INIT_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+ signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+ signal buf_to_hub_INIT_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+ signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+ signal hub_to_buf_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+ signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+ signal hub_to_buf_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+ signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+ signal buf_to_hub_REPLY_DATA : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+ signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+ signal buf_to_hub_REPLY_READ : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0); \r
+ \r
+ component trb_net16_base_hub_logic is\r
+ generic (\r
+ --media interfaces\r
+ POINT_NUMBER : integer range 2 to 16 := 2;\r
+ INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+ REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+ --general settings\r
+ DATA_WIDTH : integer range 16 to 16 := 16;\r
+ NUM_WIDTH : integer range 2 to 2 := 2\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0);\r
+ INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+ INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+ INIT_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0);\r
+ INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0);\r
+ INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+ INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+ INIT_READ_IN : in std_logic_vector (POINT_NUMBER downto 0);\r
+ REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER downto 0);\r
+ REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER downto 0);\r
+ REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+ REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+ REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER downto 0);\r
+ REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER downto 0);\r
+ REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+ REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+ REPLY_READ_IN : in std_logic_vector (POINT_NUMBER downto 0);\r
+ STAT_CHANNEL : out std_logic_vector (15 downto 0);\r
+ STAT_GEN : out std_logic_vector (31 downto 0);\r
+ CTRL_CHANNEL : in std_logic_vector (31 downto 0);\r
+ CTRL_GEN : in std_logic_vector (31 downto 0) \r
+ );\r
+end component;\r
+\r
+ \r
+ component trb_net16_io_multiplexer is\r
+ generic (\r
+ DATA_WIDTH : integer := 16;\r
+ NUM_WIDTH : integer := 2;\r
+ MUX_WIDTH : integer range 1 to 5 := 3;\r
+ MUX_SECURE_MODE : integer range 0 to 1 := 0\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN: in std_logic;\r
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT: out std_logic;\r
+ MED_DATAREADY_OUT: out std_logic;\r
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN: in std_logic;\r
+ -- Internal direction port\r
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+ -- Status and control port\r
+ CTRL: in std_logic_vector (31 downto 0);\r
+ STAT: out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component trb_net16_iobuf is\r
+ generic (\r
+ INIT_DEPTH : integer := 1;\r
+ REPLY_DEPTH : integer := 1\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out\r
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word\r
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+ MED_INIT_READ_IN: in std_logic; -- Media is reading\r
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media\r
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word\r
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);\r
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media\r
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits\r
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out\r
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word\r
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading\r
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media\r
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word\r
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);\r
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media\r
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits\r
+ -- Internal direction port\r
+ INT_INIT_DATAREADY_OUT: out std_logic;\r
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word\r
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+ INT_INIT_READ_IN: in std_logic;\r
+ INT_INIT_DATAREADY_IN: in std_logic;\r
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word\r
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);\r
+ INT_INIT_READ_OUT: out std_logic;\r
+ INT_REPLY_HEADER_IN: in std_logic;\r
+ INT_REPLY_DATAREADY_OUT: out std_logic;\r
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word\r
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+ INT_REPLY_READ_IN: in std_logic;\r
+ INT_REPLY_DATAREADY_IN: in std_logic;\r
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word\r
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);\r
+ INT_REPLY_READ_OUT: out std_logic;\r
+ -- Status and control port\r
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status\r
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status\r
+ CTRL_GEN: in std_logic_vector (31 downto 0);\r
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);\r
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);\r
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ component trb_net16_base_api is\r
+ generic (\r
+ API_TYPE : integer := API_TYPE;\r
+ FIFO_TO_INT_DEPTH : integer := 1;\r
+ FIFO_TO_APL_DEPTH : integer := 1;\r
+ FIFO_TERM_BUFFER_DEPTH : integer := 0);\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- APL Transmitter port\r
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"\r
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);\r
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted\r
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full\r
+ APL_SHORT_TRANSFER_IN : in std_logic; --\r
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr\r
+ APL_SEND_IN : in std_logic; -- Release sending of the data\r
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of\r
+ -- Receiver port\r
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);\r
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM\r
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out\r
+ APL_READ_IN : in std_logic; -- Read data word\r
+ -- APL Control port\r
+ APL_RUN_OUT : out std_logic; -- Data transfer is running\r
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)\r
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);\r
+ -- Internal direction port\r
+ INT_MASTER_DATAREADY_OUT : out std_logic;\r
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word\r
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);\r
+ INT_MASTER_READ_IN : in std_logic;\r
+ INT_MASTER_DATAREADY_IN : in std_logic;\r
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word\r
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);\r
+ INT_MASTER_READ_OUT : out std_logic;\r
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR\r
+ INT_SLAVE_DATAREADY_OUT : out std_logic;\r
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word\r
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);\r
+ INT_SLAVE_READ_IN : in std_logic;\r
+ INT_SLAVE_DATAREADY_IN : in std_logic;\r
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word\r
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);\r
+ INT_SLAVE_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);\r
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+ \r
+ \r
+ \r
+begin\r
+\r
+--generate multiplexers\r
+ gen_muxes: for i in 0 to MII_NUMBER-1 generate\r
+ MPLEX: trb_net16_io_multiplexer\r
+ generic map (\r
+ DATA_WIDTH => DATA_WIDTH,\r
+ NUM_WIDTH => NUM_WIDTH,\r
+ MUX_WIDTH => MUX_WIDTH,\r
+ MUX_SECURE_MODE => MUX_SECURE_MODE\r
+ )\r
+ port map (\r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ CLK_EN => CLK_EN,\r
+ MED_DATAREADY_IN => MED_DATAREADY_IN(i*2+1 downto i*2),\r
+ MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ MED_READ_OUT => MED_READ_OUT(i*2+1 downto i*2),\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT(i*2+1 downto i*2),\r
+ MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ MED_READ_IN => MED_READ_IN(i*2+1 downto i*2),\r
+ INT_DATAREADY_OUT => m_DATAREADY_IN(i*2+1 downto i*2),\r
+ INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ INT_READ_IN => m_READ_OUT(i*2+1 downto i*2),\r
+ INT_DATAREADY_IN => m_DATAREADY_OUT(i*2+1 downto i*2),\r
+ INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ INT_READ_OUT => m_READ_IN(i*2+1 downto i*2),\r
+ CTRL => MPLEX_CTRL((i+1)*32-1) downto i*32)\r
+ );\r
+ end generate;\r
+\r
+--generate IOBufs for MII\r
+ gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate\r
+ IOBUF: trb_net16_iobuf\r
+ generic map (\r
+ INIT_DEPTH => to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)),\r
+ REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i))\r
+ )\r
+ port map (\r
+ -- Misc\r
+ CLK => CLK ,\r
+ RESET => RESET,\r
+ CLK_EN => CLK_EN,\r
+ -- Media direction port\r
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),\r
+ MED_INIT_DATA_OUT => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ MED_INIT_READ_IN => m_READ_IN(i*2),\r
+ \r
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),\r
+ MED_INIT_DATA_IN => m_DATA_�N((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),\r
+ MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3),\r
+\r
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),\r
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
+ MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),\r
+ \r
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_OUT(i*2+1),\r
+ MED_REPLY_DATA_IN => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
+ MED_REPLY_READ_OUT => m_READ_IN(i*2+1),\r
+ MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3),\r
+ \r
+ -- Internal direction port\r
+\r
+ INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),\r
+ INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INT_INIT_READ_IN => buf_to_hub_INIT_READ(i),\r
+\r
+ INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),\r
+ INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i),\r
+ \r
+ INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i),\r
+ INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),\r
+ INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i),\r
+\r
+ INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i),\r
+ INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i),\r
+\r
+ -- Status and control port\r
+ STAT_GEN => IOBUF_STAT_GEN((i+1)*32 downto i*32),\r
+ STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32 downto i*32),\r
+ STAT_INIT_BUFFER => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32),\r
+ STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32),\r
+ CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32 downto i*32),\r
+ CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32),\r
+ STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32),\r
+ STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32)\r
+ );\r
+ end generate;\r
+ \r
+ gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+ HUBLOGIC : trb_net16_base_hub_logic\r
+ generic map{\r
+ --media interfaces\r
+ POINT_NUMBER => MII_NUMBER,\r
+ INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4),\r
+ REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4),\r
+ --general settings\r
+ DATA_WIDTH => DATA_WIDTH,\r
+ NUM_WIDTH => NUM_WIDTH\r
+ )\r
+ port map(\r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ CLK_EN => CLK_EN,\r
+ INIT_DATAREADY_IN => buf_to_hub_INIT_DATAREADY(i),\r
+ INIT_DATA_IN => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INIT_PACKET_NUM_IN => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INIT_READ_OUT => buf_to_hub_INIT_READ(i),\r
+ INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),\r
+ INIT_DATA_OUT => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ INIT_PACKET_NUM_OUT => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ INIT_READ_IN => hub_to_buf_INIT_READ(i),\r
+ REPLY_HEADER_OUT => hub_to_buf_REPLY_HEADER_OUT(i),\r
+ REPLY_DATAREADY_IN => buf_to_hub_REPLY_DATAREADY(i),\r
+ REPLY_DATA_IN => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ REPLY_PACKET_NUM_IN => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ REPLY_READ_OUT => buf_to_hub_REPLY_READ(i),\r
+ REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY(i),\r
+ REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+ REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+ REPLY_READ_IN => hub_to_buf_REPLY_READ(i),\r
+ STAT_INTERFACE => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32),\r
+ STAT_GEN => HUB_STAT_GEN((i+1)*32-1 downto i*32),\r
+ CTRL_INTERFACE => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32),\r
+ CTRL_GEN => HUB_CTRL_GEN((i+1)*32-1 downto i*32)\r
+ )\r
+ end generate;\r
+ \r
+end architecture;\r
--- /dev/null
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.std_logic_ARITH.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+use work.trb_net_std.all;\r
+\r
+\r
+entity trb_net16_hub_logic is\r
+ generic (\r
+ --media interfaces\r
+ POINT_NUMBER : integer range 2 to 16 := 2;\r
+ INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+ REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+ --general settings\r
+ DATA_WIDTH : integer range 16 to 16 := 16;\r
+ NUM_WIDTH : integer range 2 to 2 := 2\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ --Internal interfaccs to IOBufs\r
+ INIT_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0);\r
+ INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+ INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+ INIT_READ_OUT : out std_logic_vector (PONUMBER downto 0);\r
+ INIT_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0);\r
+ INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+ INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+ INIT_READ_IN : in std_logic_vector (PONUMBER downto 0);\r
+ REPLY_HEADER_OUT : out std_logic_vector (PONUMBER downto 0);\r
+ REPLY_DATAREADY_IN : in std_logic_vector (PONUMBER downto 0);\r
+ REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+ REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+ REPLY_READ_OUT : out std_logic_vector (PONUMBER downto 0);\r
+ REPLY_DATAREADY_OUT : out std_logic_vector (PONUMBER downto 0);\r
+ REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+ REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+ REPLY_READ_IN : in std_logic_vector (PONUMBER downto 0);\r
+ --Status ports (for debugging)\r
+ STAT_CHANNEL : out std_logic_vector (15 downto 0);\r
+ STAT_GEN : out std_logic_vector (31 downto 0);\r
+ CTRL_CHANNEL : in std_logic_vector (31 downto 0);\r
+ CTRL_GEN : in std_logic_vector (31 downto 0) \r
+ );\r
+end entity;\r
+\r
+architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is\r
+begin\r
+--Datapool for Init-Channel\r
+ INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0);\r
+ INIT_POOL_READ <=\r
+ and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0));\r
+ \r
+ gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate\r
+ process(INIT_DATA_IN)\r
+ variable VAR_INIT_POOL_DATA : std_logic;\r
+ begin\r
+ VAR_INIT_POOL_DATA := 0;\r
+ gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop\r
+ VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i);\r
+ end loop;\r
+ INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA;\r
+ end process;\r
+ end generate;\r
+\r
+--Data for obuf output\r
+ gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate \r
+ INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i);\r
+ end generate;\r
+\r
+ gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate \r
+ INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA;\r
+ end generate; \r
+ \r
+ gen_init_read_in\r
+ \r
+ --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word\r
+ -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+ -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
+ -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= \r
+ -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) \r
+ -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA);\r
+ -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <=\r
+ -- or_all(\r
+ -- end generate;\r
+ -- end generate;\r
+\r
+ -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+ -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
+ -- process(CLK)\r
+ -- begin\r
+ -- if rising_edge(CLK) then\r
+ -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then\r
+ -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0';\r
+ -- else\r
+ -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' \r
+ -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then\r
+ -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1';\r
+ -- end if;\r
+ -- end if;\r
+ -- end if;\r
+ -- end process;\r
+ -- end generate;\r
+ -- end generate; \r
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff