inline static void iowrite32_mb(u32 val, void __iomem *addr)
{
- iowrite32be(val, addr);
+ iowrite32(val, addr);
wmb();
}
}
ad = (u32* ) ((unsigned long)priv->iomem[bar] + (unsigned long)ad);
- val = ioread32be(ad);
+ val = ioread32(ad);
rmb();
ndelay(20);
pexor_dbg(KERN_NOTICE
for (i = 0; i < sg_length; i++) {
timeout = 0;
do {
- val = ioread32be(priv->pexor.trbnet_receiver_data[channel]);
+ val = ioread32(priv->pexor.trbnet_receiver_data[channel]);
rmb();
if ((val & MASK_FIFO_TRB_ACT) == 0) {
pexor_read_buffer_ctr += ctr * 4;
/* Credential check */
volatile u32 cred1;
volatile u32 cred2;
- cred1 = ioread32be(priv->pexor.dma_debug2);
+ cred1 = ioread32(priv->pexor.dma_debug2);
rmb();
pexor_read_buffer_ctr = 0;
/* wait for dma complete */
for (loops = 0; loops < PEXOR_DMA_MAXPOLLS; loops++) {
- dmastat = ioread32be(priv->pexor.dma_control_stat);
+ dmastat = ioread32(priv->pexor.dma_control_stat);
rmb();
if ((dmastat & PEXOR_TRB_BIT_DMA_FINISHED) != 0) {
/* DMA is completed */
}
/* Check Credentials */
- cred2 = ioread32be(priv->pexor.dma_debug2);
+ cred2 = ioread32(priv->pexor.dma_debug2);
rmb();
if (cred2 != cred1) {
pexor_msg(KERN_ERR
dmaSize, (int)pexor_read_buffer_ctr);
for (i = 0; i < dmaSize; i++) {
volatile u32 val = 0;
- val = ioread32be((i % 2 == 0)
+ val = ioread32((i % 2 == 0)
? priv->pexor.dma_debug0 : priv->pexor.dma_debug1);
rmb();
pexor_msg(KERN_ERR "DMA: %d 0x%08x DEBUG:0x%08x\n", i,