unnecessary reset signals are removed - cu

diff --git a/tdc_releases/tdc_v1.1.1/Channel_200.vhd b/tdc_releases/tdc_v1.1.1/Channel_200.vhd
index 5c34a3e8b8fb2bc84d51baaa1be0fdf0163ee518..bf14fa61461aa5f1c3369246e29dfbd7e065f946 100644 (file)
--- a/tdc_releases/tdc_v1.1.1/Channel_200.vhd
+++ b/tdc_releases/tdc_v1.1.1/Channel_200.vhd
@@ -5,7 +5,7 @@
 -- File       : Channel_200.vhd
 -- Author     : c.ugur@gsi.de
 -- Created    : 2012-08-28
--- Last update: 2013-01-30
+-- Last update: 2013-03-14
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -52,7 +52,7 @@ architecture Channel_200 of Channel_200 is
   -- carry chain
   signal data_a_i      : std_logic_vector(303 downto 0);
   signal data_b_i      : std_logic_vector(303 downto 0);
-  signal result_i      : std_logic_vector(303 downto 0);
+  signal result_i      : std_logic_vector(303 downto 0) := (others => '0');
   signal ff_array_en_i : std_logic;
 
   -- hit detection
@@ -72,8 +72,8 @@ architecture Channel_200 of Channel_200 is
   signal encoder_debug_i    : std_logic_vector(31 downto 0);
 
   -- epoch counter
-  signal epoch_cntr         : std_logic_vector(27 downto 0);
-  signal epoch_cntr_up      : std_logic;
+  signal epoch_cntr         : std_logic_vector(27 downto 0) := (others => '0');
+  signal epoch_cntr_up      : std_logic := '0';
   signal epoch_capture_time : std_logic_vector(10 downto 0);
 
   -- fifo
@@ -127,9 +127,9 @@ begin  -- Channel_200
   TimeStampCapture : process (CLK_200)
   begin
     if rising_edge(CLK_200) then
-      if RESET_200 = '1' then
-        time_stamp_i <= (others => '0');
-      elsif hit_detect_reg = '1' then
+      --if RESET_200 = '1' then
+      --  time_stamp_i <= (others => '0');
+      if hit_detect_reg = '1' then
         time_stamp_i <= coarse_cntr_reg;
       end if;
     end if;
@@ -140,10 +140,10 @@ begin  -- Channel_200
   EpochCounterCapture : process (CLK_200)
   begin
     if rising_edge(CLK_200) then
-      if RESET_200 = '1' then
-        epoch_cntr    <= (others => '0');
-        epoch_cntr_up <= '0';
-      elsif coarse_cntr_reg = epoch_capture_time or DATA_FINISHED_IN = '1' then
+      --if RESET_200 = '1' then
+      --  epoch_cntr    <= (others => '0');
+      --  epoch_cntr_up <= '0';
+      if coarse_cntr_reg = epoch_capture_time or DATA_FINISHED_IN = '1' then
         epoch_cntr    <= EPOCH_COUNTER_IN;
         epoch_cntr_up <= '1';
       elsif write_epoch_i = '1' then
@@ -185,9 +185,9 @@ begin  -- Channel_200
     if rising_edge(CLK_200) then
       if RESET_200 = '1' then
         FSM_CURRENT   <= WRITE_EPOCH;
-        write_epoch_i <= '0';
-        write_data_i  <= '0';
-        fsm_debug_i   <= "00";
+        --write_epoch_i <= '0';
+        --write_data_i  <= '0';
+        --fsm_debug_i   <= "00";
       else
         FSM_CURRENT   <= FSM_NEXT;
         write_epoch_i <= write_epoch_fsm;
@@ -248,10 +248,10 @@ begin  -- Channel_200
   FifoWriteSignal : process (CLK_200)
   begin
     if rising_edge(CLK_200) then
-      if RESET_200 = '1' then
-        fifo_data_in_i <= (others => '0');
-        fifo_wr_en_i   <= '0';
-      elsif write_epoch_i = '1' then
+      --if RESET_200 = '1' then
+      --  fifo_data_in_i <= (others => '0');
+      --  fifo_wr_en_i   <= '0';
+      if write_epoch_i = '1' then
         fifo_data_in_i(31 downto 29) <= "011";
         fifo_data_in_i(28)           <= '0';
         fifo_data_in_i(27 downto 0)  <= epoch_cntr;
@@ -276,12 +276,12 @@ begin  -- Channel_200
   RegisterOutputs : process (CLK_100)
   begin
     if rising_edge(CLK_100) then
-      if RESET_100 = '1' then
-        FIFO_DATA_OUT        <= (others => '1');
-        FIFO_EMPTY_OUT       <= '0';
-        FIFO_FULL_OUT        <= '0';
-        FIFO_ALMOST_FULL_OUT <= '0';
-      else
+      --if RESET_100 = '1' then
+      --  FIFO_DATA_OUT        <= (others => '1');
+      --  FIFO_EMPTY_OUT       <= '0';
+      --  FIFO_FULL_OUT        <= '0';
+      --  FIFO_ALMOST_FULL_OUT <= '0';
+      --else
         --if first_read_i = '1' and fifo_was_full_i = '1' then
         --  FIFO_DATA_OUT <= epoch_word_first;
         --else
@@ -290,7 +290,7 @@ begin  -- Channel_200
         FIFO_EMPTY_OUT       <= fifo_empty_i;
         FIFO_FULL_OUT        <= fifo_full_i;
         FIFO_ALMOST_FULL_OUT <= fifo_almost_full_i;
-      end if;
+      --end if;
     end if;
   end process RegisterOutputs;