Still no beef ! P2p works great but no connection when a hub is in between.
The connection between source and hub is OK; there is no lock between hub and client; clock or reset problems!!
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_downstream" module="serdes_4_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 25 13:41:31.438" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_4_sync_downstream" module="serdes_4_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 13 16:08:07.351" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_4_sync_downstream.lpc" type="lpc" modified="2014 02 25 13:41:30.000"/>
- <File name="serdes_4_sync_downstream.pp" type="pp" modified="2014 02 25 13:41:30.000"/>
- <File name="serdes_4_sync_downstream.sym" type="sym" modified="2014 02 25 13:41:30.000"/>
- <File name="serdes_4_sync_downstream.tft" type="tft" modified="2014 02 25 13:41:30.000"/>
- <File name="serdes_4_sync_downstream.txt" type="pcs_module" modified="2014 02 25 13:41:30.000"/>
- <File name="serdes_4_sync_downstream.vhd" type="top_level_vhdl" modified="2014 02 25 13:41:30.000"/>
+ <File name="serdes_4_sync_downstream.lpc" type="lpc" modified="2014 05 13 16:08:01.000"/>
+ <File name="serdes_4_sync_downstream.pp" type="pp" modified="2014 05 13 16:08:01.000"/>
+ <File name="serdes_4_sync_downstream.sym" type="sym" modified="2014 05 13 16:08:01.000"/>
+ <File name="serdes_4_sync_downstream.tft" type="tft" modified="2014 05 13 16:08:01.000"/>
+ <File name="serdes_4_sync_downstream.txt" type="pcs_module" modified="2014 05 13 16:08:01.000"/>
+ <File name="serdes_4_sync_downstream.vhd" type="top_level_vhdl" modified="2014 05 13 16:08:01.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_4_sync_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/25/2014
-Time=13:41:30
+Date=05/13/2014
+Time=16:08:01
[Parameters]
Verilog=0
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=DISABLED
-_rx_fifo2=DISABLED
-_rx_fifo3=DISABLED
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
_rx_ficlk_rate0=200
_rx_ficlk_rate1=200
_rx_ficlk_rate2=200
_cc_match_mode1=1
_cc_match_mode2=1
_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=01
-_k03=01
+_k00=00
+_k01=00
+_k02=00
+_k03=00
_k10=00
_k11=00
_k12=00
CH1_TX_FIFO "DISABLED"
CH2_TX_FIFO "DISABLED"
CH3_TX_FIFO "DISABLED"
-CH0_RX_FIFO "DISABLED"
-CH1_RX_FIFO "DISABLED"
-CH2_RX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
+CH0_RX_FIFO "ENABLED"
+CH1_RX_FIFO "ENABLED"
+CH2_RX_FIFO "ENABLED"
+CH3_RX_FIFO "ENABLED"
CH0_TDRV "0"
CH1_TDRV "0"
CH2_TDRV "0"
CH1_CTC "DISABLED"
CH2_CTC "DISABLED"
CH3_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH1_CC_MATCH4 "0100011100"
-CH2_CC_MATCH4 "0100011100"
-CH3_CC_MATCH4 "0100011100"
+CH0_CC_MATCH4 "0000011100"
+CH1_CC_MATCH4 "0000011100"
+CH2_CC_MATCH4 "0000011100"
+CH3_CC_MATCH4 "0000011100"
CH0_CC_MATCH_MODE "1"
CH1_CC_MATCH_MODE "1"
CH2_CC_MATCH_MODE "1"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
hdinp_ch1, hdinn_ch1 : in std_logic;
hdoutp_ch1, hdoutn_ch1 : out std_logic;
sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
txiclk_ch1 : in std_logic;
rx_full_clk_ch1 : out std_logic;
rx_half_clk_ch1 : out std_logic;
hdinp_ch2, hdinn_ch2 : in std_logic;
hdoutp_ch2, hdoutn_ch2 : out std_logic;
sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
txiclk_ch2 : in std_logic;
rx_full_clk_ch2 : out std_logic;
rx_half_clk_ch2 : out std_logic;
hdinp_ch3, hdinn_ch3 : in std_logic;
hdoutp_ch3, hdoutn_ch3 : out std_logic;
sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
txiclk_ch3 : in std_logic;
rx_full_clk_ch3 : out std_logic;
rx_half_clk_ch3 : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => fpsc_vlo,
+ FF_RXI_CLK_0 => rxiclk_ch0,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
PCIE_PHYSTATUS_1 => open,
SCISELCH1 => sci_sel_ch1,
SCIENCH1 => fpsc_vhi,
- FF_RXI_CLK_1 => fpsc_vlo,
+ FF_RXI_CLK_1 => rxiclk_ch1,
FF_TXI_CLK_1 => txiclk_ch1,
FF_EBRD_CLK_1 => fpsc_vlo,
FF_RX_F_CLK_1 => rx_full_clk_ch1,
PCIE_PHYSTATUS_2 => open,
SCISELCH2 => sci_sel_ch2,
SCIENCH2 => fpsc_vhi,
- FF_RXI_CLK_2 => fpsc_vlo,
+ FF_RXI_CLK_2 => rxiclk_ch2,
FF_TXI_CLK_2 => txiclk_ch2,
FF_EBRD_CLK_2 => fpsc_vlo,
FF_RX_F_CLK_2 => rx_full_clk_ch2,
PCIE_PHYSTATUS_3 => open,
SCISELCH3 => sci_sel_ch3,
SCIENCH3 => fpsc_vhi,
- FF_RXI_CLK_3 => fpsc_vlo,
+ FF_RXI_CLK_3 => rxiclk_ch3,
FF_TXI_CLK_3 => txiclk_ch3,
FF_EBRD_CLK_3 => fpsc_vlo,
FF_RX_F_CLK_3 => rx_full_clk_ch3,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_hub_downstream" module="serdes_4_sync_hub_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 06 15:48:36.454" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_4_sync_hub_downstream" module="serdes_4_sync_hub_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 08 13:39:53.561" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 05 06 15:48:34.000"/>
- <File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 05 06 15:48:34.000"/>
- <File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 05 06 15:48:35.000"/>
- <File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 05 06 15:48:35.000"/>
- <File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 05 06 15:48:35.000"/>
- <File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 05 06 15:48:34.000"/>
+ <File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 05 08 13:39:51.000"/>
+ <File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 05 08 13:39:51.000"/>
+ <File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 05 08 13:39:51.000"/>
+ <File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 05 08 13:39:51.000"/>
+ <File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 05 08 13:39:51.000"/>
+ <File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 05 08 13:39:51.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_4_sync_hub_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=05/06/2014
-Time=15:48:34
+Date=05/08/2014
+Time=13:39:51
[Parameters]
Verilog=0
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH1_PROTOCOL "G8B10B"
-CH2_PROTOCOL "G8B10B"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
-CH1_MODE "RXTX"
-CH2_MODE "RXTX"
-CH3_MODE "RXTX"
-CH0_CDR_SRC "REFCLK_CORE"
-CH1_CDR_SRC "REFCLK_CORE"
-CH2_CDR_SRC "REFCLK_CORE"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
-CH1_RX_DATARATE_RANGE "MEDHIGH"
-CH2_RX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH0_RX_DATA_RATE "FULL"
-CH1_RX_DATA_RATE "FULL"
-CH2_RX_DATA_RATE "FULL"
-CH3_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH1_TX_DATA_RATE "FULL"
-CH2_TX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH1_TX_DATA_WIDTH "8"
-CH2_TX_DATA_WIDTH "8"
-CH3_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH1_RX_DATA_WIDTH "8"
-CH2_RX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH1_TX_FIFO "DISABLED"
-CH2_TX_FIFO "DISABLED"
-CH3_TX_FIFO "DISABLED"
-CH0_RX_FIFO "DISABLED"
-CH1_RX_FIFO "DISABLED"
-CH2_RX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
-CH0_TDRV "0"
-CH1_TDRV "0"
-CH2_TDRV "0"
-CH3_TDRV "0"
-#CH0_TX_FICLK_RATE 200
-#CH1_TX_FICLK_RATE 200
-#CH2_TX_FICLK_RATE 200
-#CH3_TX_FICLK_RATE 200
-#CH0_RXREFCLK_RATE "200"
-#CH1_RXREFCLK_RATE "200"
-#CH2_RXREFCLK_RATE "200"
-#CH3_RXREFCLK_RATE "200"
-#CH0_RX_FICLK_RATE 200
-#CH1_RX_FICLK_RATE 200
-#CH2_RX_FICLK_RATE 200
-#CH3_RX_FICLK_RATE 200
-CH0_TX_PRE "DISABLED"
-CH1_TX_PRE "DISABLED"
-CH2_TX_PRE "DISABLED"
-CH3_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH1_RTERM_TX "50"
-CH2_RTERM_TX "50"
-CH3_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH1_RX_EQ "DISABLED"
-CH2_RX_EQ "DISABLED"
-CH3_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH1_RTERM_RX "50"
-CH2_RTERM_RX "50"
-CH3_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH1_RX_DCC "DC"
-CH2_RX_DCC "DC"
-CH3_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
-CH1_LOS_THRESHOLD_LO "2"
-CH2_LOS_THRESHOLD_LO "2"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH1_TX_SB "DISABLED"
-CH2_TX_SB "DISABLED"
-CH3_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH1_RX_SB "DISABLED"
-CH2_RX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH1_TX_8B10B "ENABLED"
-CH2_TX_8B10B "ENABLED"
-CH3_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH1_RX_8B10B "ENABLED"
-CH2_RX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH1_COMMA_A "1100000101"
-CH2_COMMA_A "1100000101"
-CH3_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH1_COMMA_B "0011111010"
-CH2_COMMA_B "0011111010"
-CH3_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH1_COMMA_M "1111111100"
-CH2_COMMA_M "1111111100"
-CH3_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH1_RXWA "ENABLED"
-CH2_RXWA "ENABLED"
-CH3_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH1_ILSM "ENABLED"
-CH2_ILSM "ENABLED"
-CH3_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH1_CTC "DISABLED"
-CH2_CTC "DISABLED"
-CH3_CTC "DISABLED"
-CH0_CC_MATCH4 "0000011100"
-CH1_CC_MATCH4 "0000011100"
-CH2_CC_MATCH4 "0000011100"
-CH3_CC_MATCH4 "0000011100"
-CH0_CC_MATCH_MODE "1"
-CH1_CC_MATCH_MODE "1"
-CH2_CC_MATCH_MODE "1"
-CH3_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
-CH1_CC_MIN_IPG "3"
-CH2_CC_MIN_IPG "3"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH1_SSLB "DISABLED"
-CH2_SSLB "DISABLED"
-CH3_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH1_SPLBPORTS "DISABLED"
-CH2_SPLBPORTS "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-CH1_PCSLBPORTS "DISABLED"
-CH2_PCSLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200.0
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "DISABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 200.0
-#CH0_RXREFCLK_RATE "200.0"
-#CH0_RX_FICLK_RATE 200.0
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0000000000"
-CH0_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "ENABLED"
-QD_REFCK2CORE "DISABLED"
-
-
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 200
-#CH3_RXREFCLK_RATE "200"
-#CH3_RX_FICLK_RATE 200
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "DC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111100"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH4 "0100011100"
-CH3_CC_MATCH_MODE "1"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_source_downstream" module="serdes_sync_source_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 29 08:57:47.690" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_source_downstream" module="serdes_sync_source_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 13 08:58:12.850" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2014 04 29 08:57:46.000"/>
- <File name="serdes_sync_source_downstream.pp" type="pp" modified="2014 04 29 08:57:46.000"/>
- <File name="serdes_sync_source_downstream.sym" type="sym" modified="2014 04 29 08:57:46.000"/>
- <File name="serdes_sync_source_downstream.tft" type="tft" modified="2014 04 29 08:57:46.000"/>
- <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2014 04 29 08:57:46.000"/>
- <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2014 05 13 08:58:11.000"/>
+ <File name="serdes_sync_source_downstream.pp" type="pp" modified="2014 05 13 08:58:11.000"/>
+ <File name="serdes_sync_source_downstream.sym" type="sym" modified="2014 05 13 08:58:11.000"/>
+ <File name="serdes_sync_source_downstream.tft" type="tft" modified="2014 05 13 08:58:11.000"/>
+ <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2014 05 13 08:58:11.000"/>
+ <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2014 05 13 08:58:11.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_source_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/29/2014
-Time=08:57:46
+Date=05/13/2014
+Time=08:58:11
[Parameters]
Verilog=0
_cc_match_mode1=1
_cc_match_mode2=1
_cc_match_mode3=1
-_k00=01
+_k00=00
_k01=00
_k02=00
_k03=00
CH0_RX_EQ "DISABLED"
CH0_RTERM_RX "50"
CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "3"
+CH0_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
CH0_RXWA "ENABLED"
CH0_ILSM "ENABLED"
CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
+CH0_CC_MATCH4 "0000011100"
CH0_CC_MATCH_MODE "1"
CH0_CC_MIN_IPG "3"
CCHMARK "9"
GENERIC (USER_CONFIG_FILE : String := "serdes_sync_source_downstream.txt");
port (
------------------
--- CH0 --
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
rx_cdr_lol_ch0_s : out std_logic;
tx_div2_mode_ch0_c : in std_logic;
rx_div2_mode_ch0_c : in std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
---- Miscillaneous ports
sci_wrdata : in std_logic_vector (7 downto 0);
sci_addr : in std_logic_vector (5 downto 0);
entity med_ecp3_sfp_4_sync_down is
generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
---------------------------------------------------------------------------------------------------------------------------------------------------------
MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
MED_READ_IN : in std_logic_vector(3 downto 0);
-
+ CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
-component DCS
--- synthesis translate_off
-generic
- (
- DCSMODE : string :=“POS”
- );
--- synthesis translate_on
-port (
- CLK0 : in std_logic ;
- CLK1 : in std_logic ;
- SEL : in std_logic ;
- DCSOUT : out std_logic) ;
-end component;
-
-
+signal clk_200_osc : std_logic;
+signal clk_200_tx_data : std_logic;
signal clk_200_i : std_logic_vector(3 downto 0);
-signal clk_200_internal : std_logic_vector(3 downto 0);
signal clk_rx_full : std_logic_vector(3 downto 0);
signal clk_rx_half : std_logic_vector(3 downto 0);
signal clk_tx_full : std_logic_vector(3 downto 0);
signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
signal rst_n : t_HUB_BIT;
signal rst : t_HUB_BIT; -- PL!
signal rx_serdes_rst : t_HUB_BIT;
signal tx_pll_lol : t_HUB_BIT;
signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
+signal sci_ch_i : std_logic_vector(3 downto 0);
+signal sci_qd_i : std_logic;
+signal sci_reg_i : std_logic;
+signal sci_addr_i : std_logic_vector(8 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+signal sci_write_shift_i : std_logic_vector(2 downto 0);
+signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+clk_200_osc <= OSCCLK; -- This external clock is oscillator/pll generated !!!
+clk_200_tx_data <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
+
gen_clocks : for i in 0 to 3 generate
rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
- clk_200_internal(i) <= CLK; -- This external clock is the rx_fulll of the uplink !!!
CLK_RX_FULL_OUT(i) <= clk_rx_full(i);
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
- clk_200_i(i) <= CLK; --clk_rx_full(i);
--- end generate;
+ gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+ clk_200_i(i) <= clk_rx_full(i);
+ end generate;
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i(i) <= clk_200_internal(i);
--- end generate;
+ gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+ clk_200_i(i) <= clk_200_tx_data;
+ end generate;
end generate;
-
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : entity work.serdes_4_sync_hub_downstream
+THE_SERDES : entity work.serdes_4_sync_downstream
port map(
-- CHANNEL0 --
hdinp_ch0 => SD_RXD_P_IN(0),
hdinn_ch0 => SD_RXD_N_IN(0),
hdoutp_ch0 => SD_TXD_P_OUT(0),
hdoutn_ch0 => SD_TXD_N_OUT(0),
+ rxiclk_ch0 => clk_200_i(0),
sci_sel_ch0 => sci_ch_i(0),
- txiclk_ch0 => clk_200_i(0),
+ txiclk_ch0 => clk_200_tx_data,
rx_full_clk_ch0 => clk_rx_full(0),
rx_half_clk_ch0 => clk_rx_half(0),
tx_full_clk_ch0 => clk_tx_full(0),
tx_half_clk_ch0 => clk_tx_half(0),
- fpga_rxrefclk_ch0 => clk_200_internal(0),
+ fpga_rxrefclk_ch0 => clk_200_osc,
txdata_ch0 => tx_data(0),
tx_k_ch0 => tx_k(0),
tx_force_disp_ch0 => '0',
hdinn_ch1 => SD_RXD_N_IN(1),
hdoutp_ch1 => SD_TXD_P_OUT(1),
hdoutn_ch1 => SD_TXD_N_OUT(1),
+ rxiclk_ch1 => clk_200_i(1),
sci_sel_ch1 => sci_ch_i(1),
- txiclk_ch1 => clk_200_i(1),
+ txiclk_ch1 => clk_200_tx_data,
rx_full_clk_ch1 => clk_rx_full(1),
rx_half_clk_ch1 => clk_rx_half(1),
tx_full_clk_ch1 => clk_tx_full(1),
tx_half_clk_ch1 => clk_tx_half(1),
- fpga_rxrefclk_ch1 => clk_200_internal(1),
+ fpga_rxrefclk_ch1 => clk_200_osc,
txdata_ch1 => tx_data(1),
tx_k_ch1 => tx_k(1),
tx_force_disp_ch1 => '0',
hdinn_ch2 => SD_RXD_N_IN(2),
hdoutp_ch2 => SD_TXD_P_OUT(2),
hdoutn_ch2 => SD_TXD_N_OUT(2),
+ rxiclk_ch2 => clk_200_i(2),
sci_sel_ch2 => sci_ch_i(2),
- txiclk_ch2 => clk_200_i(2),
+ txiclk_ch2 => clk_200_tx_data,
rx_full_clk_ch2 => clk_rx_full(2),
rx_half_clk_ch2 => clk_rx_half(2),
tx_full_clk_ch2 => clk_tx_full(2),
tx_half_clk_ch2 => clk_tx_half(2),
- fpga_rxrefclk_ch2 => clk_200_internal(2),
+ fpga_rxrefclk_ch2 => clk_200_osc,
txdata_ch2 => tx_data(2),
tx_k_ch2 => tx_k(2),
tx_force_disp_ch2 => '0',
hdinn_ch3 => SD_RXD_N_IN(3),
hdoutp_ch3 => SD_TXD_P_OUT(3),
hdoutn_ch3 => SD_TXD_N_OUT(3),
+ rxiclk_ch3 => clk_200_i(3),
sci_sel_ch3 => sci_ch_i(3),
- txiclk_ch3 => clk_200_i(3),
+ txiclk_ch3 => clk_200_tx_data,
rx_full_clk_ch3 => clk_rx_full(3),
rx_half_clk_ch3 => clk_rx_half(3),
tx_full_clk_ch3 => clk_tx_full(3),
tx_half_clk_ch3 => clk_tx_half(3),
- fpga_rxrefclk_ch3 => clk_200_internal(3),
+ fpga_rxrefclk_ch3 => clk_200_osc,
txdata_ch3 => tx_data(3),
tx_k_ch3 => tx_k(3),
tx_force_disp_ch3 => '0',
sci_rd => sci_read_i,
sci_wrn => sci_write_i,
- fpga_txrefclk => clk_200_i(0),
+ fpga_txrefclk => clk_200_osc, --clk_200_i(0),
tx_serdes_rst_c => tx_serdes_rst(0),
tx_pll_lol_qd_s => tx_pll_lol_quad,
tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n(i),
- RX_REFCLK => clk_200_i(i),
+ RX_REFCLK => clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
TX_PLL_LOL_QD_S => tx_pll_lol(i),
RX_SERDES_RST_CH_C => rx_serdes_rst(i),
RX_CDR_LOL_CH_S => rx_cdr_lol(i),
THE_TX_FSM : tx_reset_fsm
port map(
RST_N => rst_n(i),
- TX_REFCLK => clk_200_internal(i),
+ TX_REFCLK => clk_200_osc,
TX_PLL_LOL_QD_S => tx_pll_lol(i),
RST_QD_C => rst_qd(i),
TX_PCS_RST_CH_C => tx_pcs_rst(i),
PROC_ALLOW : process(clk_200_i(i))
begin
- if rising_edge(clk_200_i(i)) then
+ if rising_edge(clk_200_i(i)) then -- clk_200_tx_data ??
if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
rx_allow(i) <= '1';
tx_allow(i) <= '1';
tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
- PROC_START_TIMER : process(clk_200_i(i))
+ PROC_START_TIMER : process(clk_200_i(i)) --clk_200_tx_data??
begin
if rising_edge(clk_200_i(i)) then
if got_link_ready_i(i) = '1' then
-------------------------------------------------
THE_TX : soda_tx_control
port map(
- CLK_200 => clk_200_i(i),
+ CLK_200 => clk_200_i(i), --clk_200_tx_data??
CLK_100 => SYSCLK,
RESET_IN => rst(i), --CLEAR, PL!
-------------------------------------------------
THE_RX_CONTROL : rx_control
port map(
- CLK_200 => clk_rx_full(i), --clk_200_i, PL!
+ CLK_200 => clk_200_i(i), --PL!
CLK_100 => SYSCLK,
RESET_IN => rst(i), --CLEAR, PL!
STAT_OP(i)(6) <= make_link_reset_i(i);
STAT_OP(i)(5) <= request_retr_i(i);
STAT_OP(i)(4) <= start_retr_i(i);
- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";\r
+ STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
end generate;
end med_ecp3_sfp_4_sync_down_arch;
\ No newline at end of file
use work.med_sync_define.all;
use work.soda_components.all;
+
entity med_ecp3_sfp_sync_down is
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
DCSMODE : string :=“POS”
);
-- synthesis translate_on
-
port (
-CLK0 :in std_logic ;
-CLK1 :in std_logic ;
-SEL :in std_logic ;
-DCSOUT :out std_logic) ;
+ CLK0 :in std_logic ;
+ CLK1 :in std_logic ;
+ SEL :in std_logic ;
+ DCSOUT :out std_logic) ;
end component;
-
---signal refclk_p_in_S : std_logic; --PL!
---signal refclk_n_in_S : std_logic; --PL!
---signal refclk2core_S : std_logic; --PL!
-
signal clk_200_i : std_logic;
signal clk_200_internal : std_logic;
signal clk_rx_full : std_logic;
CLK_TX_HALF_OUT <= clk_tx_half;
CLK_TX_FULL_OUT <= clk_tx_full;
-
-
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
rst_n <= not(CLEAR or internal_make_link_reset_out);
rst <= (CLEAR or internal_make_link_reset_out);
-
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
clk_200_i <= clk_rx_full;
end generate;
-------------------------------------------------
THE_SERDES : entity work.serdes_sync_source_downstream
port map(
--- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL!
--- refclkn => PCSA_REFCLKN, -- external refclock straight into serdes PL!
hdinp_ch0 => SD_RXD_P_IN,
hdinn_ch0 => SD_RXD_N_IN,
hdoutp_ch0 => SD_TXD_P_OUT,
STAT_OP(5) <= request_retr_i;
STAT_OP(4) <= start_retr_i;
STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_down_arch;
+end med_ecp3_sfp_sync_down_arch;
\ No newline at end of file
signal got_link_ready_i : std_logic;
signal internal_make_link_reset_out : std_logic;
+attribute syn_preserve of wa_position : signal is true;
+attribute syn_keep of wa_position : signal is true;
+attribute syn_preserve of wa_position_rx : signal is true;
+attribute syn_keep of wa_position_rx : signal is true;
+
signal stat_rx_control_i : std_logic_vector(31 downto 0);
signal stat_tx_control_i : std_logic_vector(31 downto 0);
signal debug_rx_control_i : std_logic_vector(31 downto 0);
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
---------------------------------------------------------------------------------------------------------------------------------------------------------
MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
MED_READ_IN : in std_logic_vector(3 downto 0);
-
+ CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
CLOCK_OUT : out std_logic
);
end component;\r
+\r
+component DCS
+-- synthesis translate_off
+generic
+ (
+ DCSMODE : string :=“POS”
+ );
+-- synthesis translate_on
+port (
+ CLK0 : in std_logic ;
+ CLK1 : in std_logic ;
+ SEL : in std_logic ;
+ DCSOUT : out std_logic) ;
+end component;
end package;
\ No newline at end of file
###==== BEGIN Header
# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-# Written on Wed Dec 18 11:52:15 2013
-# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor
+# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc
+# Written on Tue May 20 15:36:03 2014
+# by Synplify Pro, I-2013.09L FDC Constraint Editor
# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.
define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable
###==== END Collections
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0}
-create_clock -name {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5}\r
-\r
-
-set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} }
-set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} }
+create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add
+create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add
+create_clock -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
+create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add
+create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add
+create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add
+create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
###==== END Clocks
###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"
###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"
+
+
+
+
+
+
+
signal soda_counter_i : unsigned(3 downto 0);
attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
- attribute syn_preserve of soda_rx_clock_full : signal is true;
- attribute syn_keep of soda_rx_clock_full : signal is true;
- attribute syn_preserve of soda_rx_clock_half : signal is true;
- attribute syn_keep of soda_rx_clock_half : signal is true;
+ attribute syn_preserve of clk_soda_i : signal is true;
+ attribute syn_keep of clk_soda_i : signal is true;
+-- attribute syn_preserve of soda_rx_clock_full : signal is true;
+-- attribute syn_keep of soda_rx_clock_full : signal is true;
+-- attribute syn_preserve of soda_rx_clock_half : signal is true;
+-- attribute syn_keep of soda_rx_clock_half : signal is true;
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
attribute syn_preserve of clk_raw_internal : signal is true;
soda_counter_i <= soda_counter_i+1;
end if;
end process;
- \r
- TEST_LINE(0) <= time_counter(1);\r
+
+ TEST_LINE(0) <= time_counter(1);
TEST_LINE(1) <= '0';
TEST_LINE(2) <= '0';
TEST_LINE(3) <= soda_counter_i(2);
TEST_LINE(4) <= '0';
- TEST_LINE(5) <= '0';\r
+ TEST_LINE(5) <= '0';
TEST_LINE(6) <= soda_rx_clock_half;
TEST_LINE(7) <= '0';
TEST_LINE(8) <= '0';
-\r
+
TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating
-- attribute syn_useioff of FLASH_DOUT : signal is true;
-- attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_keep of soda_counter_i : signal is true;
+ attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
- attribute syn_preserve of soda_rxup_clock_full : signal is true;
- attribute syn_keep of soda_rxup_clock_full : signal is true;
-
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
attribute syn_preserve of clk_raw_internal : signal is true;
attribute syn_keep of clk_raw_internal : signal is true;
- attribute syn_preserve of clk_soda_i : signal is true;
- attribute syn_keep of clk_soda_i : signal is true;
- attribute syn_preserve of txup_dlm_i : signal is true;
- attribute syn_keep of txup_dlm_i : signal is true;
- attribute syn_preserve of rxup_dlm_i : signal is true;
- attribute syn_keep of rxup_dlm_i : signal is true;
- attribute syn_preserve of txdn_dlm_i : signal is true;
- attribute syn_keep of txdn_dlm_i : signal is true;
- attribute syn_preserve of rxdn_dlm_i : signal is true;
- attribute syn_keep of rxdn_dlm_i : signal is true;
+ attribute syn_preserve of clk_soda_i : signal is true;
+ attribute syn_keep of clk_soda_i : signal is true;
+ attribute syn_preserve of txup_dlm_i : signal is true;
+ attribute syn_keep of txup_dlm_i : signal is true;
+ attribute syn_preserve of rxup_dlm_i : signal is true;
+ attribute syn_keep of rxup_dlm_i : signal is true;
+ attribute syn_preserve of txdn_dlm_i : signal is true;
+ attribute syn_keep of txdn_dlm_i : signal is true;
+ attribute syn_preserve of rxdn_dlm_i : signal is true;
+ attribute syn_keep of rxdn_dlm_i : signal is true;
begin
IS_SYNC_SLAVE => c_NO
)
port map(
- CLK => clk_soda_i, --clk_raw_internal, --clk_200_i,
+ OSCCLK => clk_raw_internal,
+ TX_DATACLK => clk_soda_i, --clk_raw_internal, --clk_200_i,
SYSCLK => clk_sys_internal, --clk_sys_i,
RESET => reset_i,
CLEAR => clear_i,
MED_READ_IN(2) => med_read_out(2),
MED_READ_IN(3) => med_read_out(4),
+ CLK_RX_HALF_OUT(0) => open,
+ CLK_RX_HALF_OUT(1) => open,
+ CLK_RX_HALF_OUT(2) => open,
+ CLK_RX_HALF_OUT(3) => open,
+
CLK_RX_FULL_OUT(0) => soda_rxdn_clock_full(0), -- needed for sync replies i.e. calibration
CLK_RX_FULL_OUT(1) => soda_rxdn_clock_full(1), -- needed for sync replies i.e. calibration
CLK_RX_FULL_OUT(2) => soda_rxdn_clock_full(2), -- needed for sync replies i.e. calibration
CLK_RX_FULL_OUT(3) => soda_rxdn_clock_full(3), -- needed for sync replies i.e. calibration
+ CLK_TX_HALF_OUT(0) => open,
+ CLK_TX_HALF_OUT(1) => open,
+ CLK_TX_HALF_OUT(2) => open,
+ CLK_TX_HALF_OUT(3) => open,
+
+ CLK_TX_FULL_OUT(0) => open,
+ CLK_TX_FULL_OUT(1) => open,
+ CLK_TX_FULL_OUT(2) => open,
+ CLK_TX_FULL_OUT(3) => open,
+
RX_DLM(0) => rxdn_dlm_i(0),
RX_DLM(1) => rxdn_dlm_i(1),
RX_DLM(2) => rxdn_dlm_i(2),
RX_DLM(3) => rxdn_dlm_i(3),
--- RX_DLM_WORD(0*8+7 downto 0*8) => rxdn_dlm_word(1),
RX_DLM_WORD(0) => rxdn_dlm_word(0),
RX_DLM_WORD(1) => rxdn_dlm_word(1),
RX_DLM_WORD(2) => rxdn_dlm_word(2),
TX_DLM(2) => txdn_dlm_i(2),
TX_DLM(3) => txdn_dlm_i(3),
--- TX_DLM_WORD(0*8+7 downto 0*8) => txdn_dlm_word(1),
TX_DLM_WORD(0) => txdn_dlm_word(0),
TX_DLM_WORD(1) => txdn_dlm_word(1),
TX_DLM_WORD(2) => txdn_dlm_word(2),
SCI_NACK => sci2_nack,
--Status and control port
--- STAT_OP(0*16+15 downto 0*16) => med_stat_op(1*16+15 downto 1*16),
STAT_OP(0) => med_stat_op(1*16+15 downto 1*16),
STAT_OP(1) => med_stat_op(6*16+15 downto 6*16),
STAT_OP(2) => med_stat_op(2*16+15 downto 2*16),
STAT_OP(3) => med_stat_op(4*16+15 downto 4*16),
--- CTRL_OP(0*16+15 downto 0*16) => med_ctrl_op(1*16+15 downto 1*16),
CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16),
CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16),
CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16),
<Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodaclient"/>
</Source>
- <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
+ <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
<Options/>
</Source>
<Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
-rvl_alias "clk_soda_i" "clk_soda_i";
-RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0";
+RVL_ALIAS "clk_soda_i" "clk_soda_i";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
# SYSCONFIG MCCLK_FREQ = 2.5;
# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
- FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
#################################################################
# Clock I/O
#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
DEFINE PORT GROUP "CLK_group" "CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ;
#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
BLOCK JTAGPATHS ;
## IOBUF ALLPORTS ;
-#USE SECONDARY NET "reveal_ist_260" ;
-USE PRIMARY NET "clk_raw_internal" ;
-USE PRIMARY NET "clk_sys_internal" ;
-#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ;
-#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ;
-#USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-USE PRIMARY NET "soda_rx_clock_full" ;
-USE PRIMARY NET "soda_rx_clock_half" ;
+USE PRIMARY NET "clk_raw_internal_c" ;
+USE PRIMARY NET "clk_sys_internal_c" ;
+USE PRIMARY NET "clk_soda_i" ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-05-06">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-05-22">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2035084698" Name="trb3_periph_sodahub_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2037156685" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
- <Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <Clock SampleClk="the_hub_sync_downlink/oscclk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Bus Name="sfp_los">
- <Sig Type="SIG" Name="sfp_los:1"/>
- <Sig Type="SIG" Name="sfp_los:2"/>
- <Sig Type="SIG" Name="sfp_los:3"/>
- <Sig Type="SIG" Name="sfp_los:4"/>
- <Sig Type="SIG" Name="sfp_los:5"/>
- <Sig Type="SIG" Name="sfp_los:6"/>
- </Bus>
- <Bus Name="sfp_txdis">
- <Sig Type="SIG" Name="sfp_txdis:1"/>
- <Sig Type="SIG" Name="sfp_txdis:2"/>
- <Sig Type="SIG" Name="sfp_txdis:3"/>
- <Sig Type="SIG" Name="sfp_txdis:4"/>
- <Sig Type="SIG" Name="sfp_txdis:5"/>
- <Sig Type="SIG" Name="sfp_txdis:6"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rst_n"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_allow_q"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_cdr_lol"/>
+ <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
<Bus Name="the_hub_sync_uplink/rx_data">
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
</Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
- <Bus Name="the_hub_sync_uplink/rx_dlm_word">
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_hub_sync_uplink/rx_fsm_state">
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_allow_q"/>
- <Bus Name="the_hub_sync_uplink/tx_data">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
- <Bus Name="the_hub_sync_uplink/tx_dlm_word">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_hub_sync_uplink/tx_fsm_state">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_serdes_rst"/>
- <Bus Name="a_soda_hub/super_burst_nr_s">
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:0"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:1"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:2"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:3"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:4"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:5"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:6"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:7"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:8"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:9"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:10"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:11"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:12"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:13"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:14"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:15"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:16"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:17"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:18"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:19"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:20"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:21"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:22"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:23"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:24"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:25"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:26"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:27"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:28"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:29"/>
- <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:30"/>
- </Bus>
- <Bus Name="a_soda_hub/rxdn_dlm_in">
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:0"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:1"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:2"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:3"/>
- </Bus>
- <Bus Name="a_soda_hub/rxdn_dlm_word_in[3:0]">
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:0"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:1"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:2"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:3"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:4"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:5"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:6"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:7"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:0"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:1"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:2"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:3"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:4"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:5"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:6"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:7"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:0"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:1"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:2"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:3"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:4"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:5"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:6"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:7"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:0"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:1"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:2"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:3"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:4"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:5"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:6"/>
- <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:7"/>
- </Bus>
- <Bus Name="a_soda_hub/txdn_dlm_out">
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:0"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:1"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:2"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:3"/>
- </Bus>
- <Bus Name="a_soda_hub/txdn_dlm_word_out[3:0]">
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:0"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:1"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:2"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:3"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:4"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:5"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:6"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:7"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:0"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:1"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:2"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:3"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:4"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:5"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:6"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:7"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:0"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:1"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:2"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:3"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:4"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:5"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:6"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:7"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:0"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:1"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:2"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:3"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:4"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:5"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:6"/>
- <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/watchdog_trigger">
- <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/sd_los_in">
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/sd_txdis_out">
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:3"/>
- </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/got_link_ready"/>
+ <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_data_in:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/reg_rx_k_in"/>
+ <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_data_in:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_control/rx_k_in"/>
+ <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/cs:2"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/rx_los_low_ch_s"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_rx_fsm/tx_pll_lol_qd_s"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/rx_allow_qtx"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_allow_qtx"/>
+ <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_data_out:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx/tx_k_out"/>
+ <Bus Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/cs:2"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/lsm_status:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/\generated_logic(0)\/the_tx_fsm/rst_n"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_hub_sync_uplink/lsm_status,"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="(BUS)the_hub_sync_uplink/rx_fsm_state[3:0],"/>
<TU Serialbits="0" Type="0" ID="2" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/start_timer:18,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/rx_error,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="the_hub_sync_uplink/got_link_ready_i,"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="a_soda_hub/start_of_superburst_s,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="a_soda_hub/start_of_superburst_s,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/got_link_ready_i,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="code/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="code/ip/serdes_sync_source_downstream.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/serdes_sync_source_downstream.lpc" type="LPC_Module" type_short="LPC">
+ <Options/>
+ </Source>
<Source name="code/ip/serdes_sync_source_downstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
#################################################################
# Clock I/O
#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
#################################################################
# Basic Settings
#################################################################
- SYSCONFIG MCCLK_FREQ=20 ;
- FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+SYSCONFIG MCCLK_FREQ=20 ;
# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE TO CELL "THE_SODA_SOURCE.packet_builder.soda_cmd_word_S*" 10.000000 ns ;
BLOCK JTAGPATHS ;
## IOBUF ALLPORTS ;
#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-
-FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ;
-FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ;
-FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ;
-FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ;
-USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ;
-USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ;
-USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ;
-USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ;
-\r
+#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
+#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ;
+#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ;
+#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ;
+#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ;
+#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ;
+#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ;
+#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ;
+#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ;
+USE PRIMARY NET "THE_SYNC_LINK/CLK_RX_FULL_OUT_c" ;
+USE PRIMARY NET "clk_sys_internal_c" ;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-04-30">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-05-22">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2034025010" Name="trb3_periph_sodasource_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2037164429" Name="trb3_periph_sodasource_LA0" ID="0">
<Setting>
<Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="1" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
- <FileTime>05/06/14 09:58:37</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140522.bit</File>
+ <FileTime>05/22/14 13:40:45</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140506.bit</File>
- <FileTime>05/06/14 09:54:42</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140522.bit</File>
+ <FileTime>05/22/14 10:56:23</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
- <FileTime>05/06/14 11:55:27</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140513.bit</File>
+ <FileTime>05/13/14 09:58:14</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
- <FileTime>05/06/14 11:55:27</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140513.bit</File>
+ <FileTime>05/13/14 09:58:14</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="2.1.0">
+<ispXCF version="3.1.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
- <FileTime>09/24/13 10:52:51</FileTime>
- <Operation>Bypass</Operation>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
+ <SVFProcessor>ispVM</SVFProcessor>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140506.bit</File>
- <FileTime>05/06/14 12:42:05</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140522.bit</File>
+ <FileTime>05/22/14 14:50:45</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
- <FileTime>09/03/13 16:32:30</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
- <Operation>Bypass</Operation>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit</File>
- <FileTime>04/10/13 14:12:21</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
- <Operation>Bypass</Operation>
+ <Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
- <Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140506.bit</File>
- <FileTime>05/06/14 12:04:36</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140522.bit</File>
+ <FileTime>05/22/14 14:25:11</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
+ <SVFProcessor>ispVM</SVFProcessor>
<Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Bypass</Operation>
+ <Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>32</PreloadLength>
- <IOVectorData>0x00000000</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
<BScanVal>0</BScanVal>
</Bypass>
<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140430.bit</File>
- <FileTime>04/30/14 10:18:14</FileTime>
+ <FileTime>04/30/14 15:40:52</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140430.bit</File>
- <FileTime>04/30/14 10:16:11</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140514.bit</File>
+ <FileTime>05/14/14 10:02:39</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
jspc29 / soda.git / commitdiff