new hub register to store status of slow control hub logic at reset

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 7b3f0c40a7694372b5250376022feab5568c3095..3f3416feea48a09fa52967d0181f4d4eb390688a 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -178,6 +178,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal HUB_STAT_ERRORBITS        : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
   signal buf_HUB_STAT_CHANNEL      : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
   signal buf_STAT_POINTS_locked    : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
+  signal HUB_STAT_after_reset      : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
   signal buf_STAT_DEBUG            : std_logic_vector (31 downto 0);
   signal buf_CTRL_DEBUG            : std_logic_vector (31 downto 0);
   signal buf_MED_DATAREADY_OUT     : std_logic_vector (MII_NUMBER-1 downto 0);
@@ -964,6 +965,7 @@ end generate;
             STAT_TIMEOUT          => STAT_TIMEOUT((i+1)*32-1 downto i*32),
             STAT_ERRORBITS        => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32),
             STAT_ALL_ERRORBITS    => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16),
+            STAT_after_reset      => HUB_STAT_after_reset((i+1)*32-1 downto i*32),
             CTRL_TIMEOUT_TIME     => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
             CTRL_activepoints     => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
             CTRL_DISABLED_PORTS   => hub_ctrl_disabled_ports,
@@ -1363,7 +1365,9 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
   buf_HC_STAT_REGS(30*32+31 downto 16*32+MII_NUMBER) <= (others => '0');
   buf_HC_STAT_REGS(31*32+31 downto 31*32)            <= buf_HUB_MISMATCH_PATTERN;
   buf_HC_STAT_REGS(35*32+31 downto 32*32)            <= HUB_STAT_ERRORBITS;
-  buf_HC_STAT_REGS(63*32+31 downto 36*32)            <= (others => '0');
+  buf_HC_STAT_REGS(38*32+31 downto 36*32)            <= (others => '0');
+  buf_HC_STAT_REGS(39*32+31 downto 39*32)            <= HUB_STAT_after_reset(127 downto 96); 
+  buf_HC_STAT_REGS(63*32+31 downto 40*32)            <= (others => '0');
 
   loop_links : for i in 0 to 16 generate
     buf_HC_STAT_REGS(5*32+i) <= '1' when MII_IS_UPLINK(i) = 1 else '0'; --(i < MII_NUMBER or (i = MII_NUMBER and INT_NUMBER > 0)) and

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index c3ca10959b4f6d60ee005a628a58b89fd367e9d2..ac82c277a7a4614516a31d042523070f3fc7eaaf 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -375,6 +375,7 @@ component trb_net16_hub_streaming_port is
       STAT_POINTS_locked    : out std_logic_vector (31 downto 0);
       STAT_TIMEOUT          : out std_logic_vector (31 downto 0);
       STAT_ERRORBITS        : out std_logic_vector (31 downto 0);
+      STAT_after_reset      : out std_logic_vector (31 downto 0);
       STAT_ALL_ERRORBITS    : out std_logic_vector (16*32-1 downto 0);
       CTRL_TIMEOUT_TIME     : in  std_logic_vector (15 downto 0);
       CTRL_activepoints     : in  std_logic_vector (31 downto 0);

diff --git a/trb_net16_hub_logic_2.vhd b/trb_net16_hub_logic_2.vhd
index 42501aa0e7fd7afd4158aded83b093f070d8d419..be0631b62bcfd8f19209ab5462d3bc7c31fe9148 100644 (file)
--- a/trb_net16_hub_logic_2.vhd
+++ b/trb_net16_hub_logic_2.vhd
@@ -42,6 +42,7 @@ entity trb_net16_hub_logic is
     STAT_TIMEOUT       : out std_logic_vector (31 downto 0);
     STAT_ERRORBITS     : out std_logic_vector (31 downto 0);
     STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0);
+    STAT_after_reset   : out std_logic_vector (31 downto 0);
     CTRL_TIMEOUT_TIME  : in  std_logic_vector (15 downto 0);
     CTRL_activepoints  : in  std_logic_vector (31 downto 0) := (others => '1');
     CTRL_DISABLED_PORTS: in  std_logic_vector (31 downto 0) := (others => '0');
@@ -59,7 +60,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
   signal config_wait_free_init_pool : unsigned(31 downto 0) := x"00010000"; --65ms
   signal config_wait_reply          : unsigned(31 downto 0) := x"00000400"; -- 1ms
 
-  signal reset_i                 : std_logic;
+  signal reset_i, last_reset_i   : std_logic;
   signal timer_ms_tick           : std_logic;
   signal timer_us_tick           : std_logic;
   signal timer_us_reset          : std_logic;
@@ -147,6 +148,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
   signal timeout_ports_disable           : std_logic_vector(POINT_NUMBER-1 downto 0)    := (others => '0');
   attribute syn_keep of reset_i : signal is true;  
   
+  signal buf_STAT                        : std_logic_vector(15 downto 0);
+  
 begin
 
 ----------------------------------
@@ -541,6 +544,16 @@ process(reply_pool_free, reply_open,act_reply_port)
 ----------------------------------
 --Status registers
 ----------------------------------  
+   
+  PROC_SAVE_STATE : process begin
+    wait until rising_edge(CLK);
+    last_reset_i <= reset_i;
+    if reset_i = '1' and last_reset_i = '0' then
+      STAT_after_reset(15 downto  0) <= STAT_POINTS_locked(15 downto 0);
+      STAT_after_reset(19 downto 16) <= buf_STAT(3 downto 0);
+      STAT_after_reset(23 downto 20) <= std_logic_vector(to_unsigned(act_reply_port,4));
+    end if;
+  end process;
   
   STAT_POINTS_locked(31 downto POINT_NUMBER)  <= (others => '0');
 
@@ -566,6 +579,10 @@ process(reply_pool_free, reply_open,act_reply_port)
           elsif reading_trmF2(i) = '1' then
             STAT_ALL_ERRORBITS(i*32+15 downto i*32+0) <= REPLY_DATA_IN(i*16+15 downto i*16);
           end if;
+          if reset_i = '1' then
+            STAT_ALL_ERRORBITS(i*32+4) <= '0';  --reset trace bit
+            STAT_ALL_ERRORBITS(i*32+0) <= '0';  --reset answer bit
+          end if;        
         end loop;
       end if;
     end process;
@@ -582,18 +599,19 @@ process(reply_pool_free, reply_open,act_reply_port)
   PROC_FSMstate : process begin
     wait until rising_edge(CLK);
       case currentstate is
-        when IDLE => STAT(3 downto 0) <= x"1"; 
-        when SELECT_INIT => STAT(3 downto 0) <= x"2"; 
-        when FORWARD_INIT => STAT(3 downto 0) <= x"3"; 
-        when SELECT_REPLY => STAT(3 downto 0) <= x"4"; 
-        when WAIT_FOR_SELECT => STAT(3 downto 0) <= x"5"; 
-        when FORWARD_REPLY => STAT(3 downto 0) <= x"6"; 
-        when REPLY_TIMEOUT => STAT(3 downto 0) <= x"7"; 
-        when SEND_TRM => STAT(3 downto 0) <= x"8"; 
-        when FINISHED => STAT(3 downto 0) <= x"F"; 
+        when IDLE => buf_STAT(3 downto 0) <= x"1"; 
+        when SELECT_INIT => buf_STAT(3 downto 0) <= x"2"; 
+        when FORWARD_INIT => buf_STAT(3 downto 0) <= x"3"; 
+        when SELECT_REPLY => buf_STAT(3 downto 0) <= x"4"; 
+        when WAIT_FOR_SELECT => buf_STAT(3 downto 0) <= x"5"; 
+        when FORWARD_REPLY => buf_STAT(3 downto 0) <= x"6"; 
+        when REPLY_TIMEOUT => buf_STAT(3 downto 0) <= x"7"; 
+        when SEND_TRM => buf_STAT(3 downto 0) <= x"8"; 
+        when FINISHED => buf_STAT(3 downto 0) <= x"F"; 
       end case;
     end process;
   
+STAT <= buf_STAT;  
   
 end architecture;