added clock for power converters to central FPGA

diff --git a/base/cores/pll_200_4.ipx b/base/cores/pll_200_4.ipx
index bb2e14c4cbd1093f4b5f956793c9638e92e165d3..278881d0a95baf8e40a1473ed1e38c0b2b77b861 100644 (file)
--- a/base/cores/pll_200_4.ipx
+++ b/base/cores/pll_200_4.ipx
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_200_4" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 09 30 15:30:43.801" version="5.6" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="pll_200_4" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 10 07 15:22:33.407" version="5.3" type="Module" synthesis="" source_format="VHDL">
   <Package>
-               <File name="pll_200_4.lpc" type="lpc" modified="2014 09 30 15:30:30.000"/>
-               <File name="pll_200_4.vhd" type="top_level_vhdl" modified="2014 09 30 15:30:30.000"/>
-               <File name="pll_200_4_tmpl.vhd" type="template_vhdl" modified="2014 09 30 15:30:30.000"/>
+               <File name="pll_200_4.lpc" type="lpc" modified="2014 10 07 15:22:29.000"/>
+               <File name="pll_200_4.vhd" type="top_level_vhdl" modified="2014 10 07 15:22:29.000"/>
+               <File name="pll_200_4_tmpl.vhd" type="template_vhdl" modified="2014 10 07 15:22:29.000"/>
   </Package>
 </DiamondModule>

diff --git a/base/cores/pll_200_4.lpc b/base/cores/pll_200_4.lpc
index 391127a272df4e309a0d5c0a36021b0c300e5e54..d9d8853ffe8ef67b990a74ed679179a94925f4e3 100644 (file)
--- a/base/cores/pll_200_4.lpc
+++ b/base/cores/pll_200_4.lpc
@@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation
 CoreType=LPM
 CoreStatus=Demo
 CoreName=PLL
-CoreRevision=5.6
+CoreRevision=5.3
 ModuleName=pll_200_4
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=09/30/2014
-Time=15:30:30
+Date=10/07/2014
+Time=15:22:29
 
 [Parameters]
 Verilog=0
@@ -54,7 +54,7 @@ U_KFrq=50
 OK_Tol=0.0
 KFrq=
 ClkRst=0
-PCDR=0
+PCDR=1
 FINDELA=0
 VcoRate=
 Bandwidth=0.856080
@@ -64,6 +64,3 @@ ClkOSBp=0
 EnCLKOK=0
 ClkOKBp=0
 enClkOK2=0
-
-[Command]
-cmd_line= -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw

diff --git a/base/cores/pll_200_4.vhd b/base/cores/pll_200_4.vhd
index 1f0bdb5bfb2869a250cc9e36a1312c095d243b6c..6259145b5fca3df8f45342be8ef83d53b7c61f32 100644 (file)
--- a/base/cores/pll_200_4.vhd
+++ b/base/cores/pll_200_4.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
--- Module  Version: 5.6
---/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw 
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.3
+--/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e 
 
--- Tue Sep 30 15:30:30 2014
+-- Tue Oct  7 15:22:29 2014
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -14,6 +14,7 @@ use ecp3.components.all;
 entity pll_200_4 is
     port (
         CLK: in std_logic; 
+        RESET: in std_logic; 
         CLKOP: out std_logic; 
         LOCK: out std_logic);
  attribute dont_touch : boolean;
@@ -75,14 +76,13 @@ begin
         PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
         CLKOK_DIV=>  2, CLKOP_DIV=>  128, CLKFB_DIV=>  1, CLKI_DIV=>  50, 
         FIN=> "200.000000")
-        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
-            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
-            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
-            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
-            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
-            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
-            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
-            CLKINTFB=>open);
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, 
+            WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, 
+            DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, 
+            DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, 
+            FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, 
+            FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, 
+            CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
 
     CLKOP <= CLKOP_t;
 end Structure;

diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd
index 106c98b7c621c00e907a07029b293f8bc983ba59..54112d86a99fd3ee648e362f94e9004e35844fa3 100644 (file)
--- a/trb3_gbe/trb3_central.vhd
+++ b/trb3_gbe/trb3_central.vhd
@@ -369,9 +369,10 @@ end generate;
 gen_power_clock : if USE_POWER_CLOCK = c_YES generate
   PLL_ENPIRION : entity work.pll_200_4
     port map(
-      CLK => clk_raw_internal,
+      CLK   => clk_raw_internal,
+      RESET => reset_i,
       CLKOP => ENPIRION_CLOCK,
-      LOCK => open
+      LOCK  => open
       );
 end generate;