Both source and client now accessible over trbnet.
No optical comm. Fiberes swapped?? Looks like both are talking on the same channel.
<Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- STAT : out std_logic_vector(31 downto 0) := (others => '0') -- DEBUG
+ LEDS_OUT : out std_logic_vector(3 downto 0)
);
end soda_client;
signal crc_valid_S : std_logic := '0';
-- Signals
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
- signal CURRENT_STATE, NEXT_STATE: STATES;
+ type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
+ signal CURRENT_STATE, NEXT_STATE: STATES;
-- slave bus signals
- signal bus_ack_x : std_logic;
- signal bus_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
- signal buf_bus_data_out : std_logic_vector(31 downto 0);
+ signal bus_ack_x : std_logic;
+ signal bus_ack : std_logic;
+ signal store_wr_x : std_logic;
+ signal store_wr : std_logic;
+ signal store_rd_x : std_logic;
+ signal store_rd : std_logic;
+ signal buf_bus_data_out : std_logic_vector(31 downto 0);
+ signal ledregister_i : std_logic_vector(31 downto 0);
begin
begin
if( rising_edge(SYSCLK) ) then
if ( RESET = '1' ) then
- elsif( (store_wr = '1') and (SODA_ADDR_IN = B"1100") ) then
+ LEDregister_i <= (others => '0');
+ elsif( (store_wr = '1') and (SODA_ADDR_IN = B"0000") ) then
+ LEDregister_i <= SODA_DATA_IN;
end if;
end if;
end process THE_WRITE_REG_PROC;
if( rising_edge(SYSCLK) ) then
if ( RESET = '1' ) then
buf_bus_data_out <= (others => '0');
- elsif( (store_rd = '1') and (SODA_ADDR_IN = B"1100") ) then
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = B"0000") ) then
buf_bus_data_out <= '0' & soda_cmd_word_S;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = B"0001") ) then
+ buf_bus_data_out <= '0' & super_burst_nr_S;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then
+ buf_bus_data_out <= LEDregister_i;
end if;
end if;
end process THE_READ_REG_PROC;
-- output signals
+ LEDS_OUT <= LEDregister_i(3 downto 0);
+
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
CLK_EN : in std_logic;
--Internal Connection
SODA_BURST_PULSE_IN : in std_logic := '0'; --
- SODA_CMD_STROBE_IN : in std_logic := '0'; --
- SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);
- TEST_LINE : out std_logic_vector(15 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
+ LEDS_OUT : out std_logic_vector(3 downto 0)
);
end component;\r
\r
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
+ LEDS_OUT : out std_logic_vector(3 downto 0)
);
end component;
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);
- TEST_LINE : out std_logic_vector(15 downto 0);
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
+ LEDS_OUT : out std_logic_vector(3 downto 0)
+-- TEST_LINE : out std_logic_vector(15 downto 0);
+-- STAT : out std_logic_vector(31 downto 0) -- DEBUG
);
end soda_source;
EXPECTED_REPLY_IN => expected_reply_S,
RX_DLM_IN => RX_DLM_IN,
RX_DLM_WORD_IN => RX_DLM_WORD_IN,
- REPLY_VALID_OUT => reply_valid_S,\r
+ REPLY_VALID_OUT => reply_valid_S,
REPLY_OK_OUT => reply_OK_S
);
-\r
- src_calibration_timer : soda_calibration_timer\r
+
+ src_calibration_timer : soda_calibration_timer
port map(
SYSCLK => SYSCLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => '1',
--Internal Connection
- START_CALIBRATION => start_calibration_S,\r
- END_CALIBRATION => reply_valid_S,\r
+ START_CALIBRATION => start_calibration_S,
+ END_CALIBRATION => reply_valid_S,
CALIB_VALID_OUT => calibration_valid_S,
- CALIB_TIME_OUT => calibration_time_S\r
+ CALIB_TIME_OUT => calibration_time_S
);
src_store_calib_proc : process(SYSCLK)
soda_cmd_strobe_S <= '0';
soda_cmd_word_S <= (others => '0');
LEDregister_i <= (others => '0');
- TEST_LINE_i <= (others => '0');
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then\r
+-- TEST_LINE_i <= (others => '0');
+ elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then
soda_cmd_strobe_S <= '1';
soda_cmd_word_S <= SODA_DATA_IN(30 downto 0);
elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then
LEDregister_i <= SODA_DATA_IN;
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then
- TEST_LINE_i <= SODA_DATA_IN;
- else\r
+-- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then
+-- TEST_LINE_i <= SODA_DATA_IN;
+ else
soda_cmd_strobe_S <= '0';
end if;
end if;
end process THE_WRITE_REG_PROC;
- LEDS_OUT <= LEDregister_i(3 downto 0);
- TEST_LINE <= TEST_LINE_i(15 downto 0);
-- register read
THE_READ_REG_PROC: process( SYSCLK )
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
buf_bus_data_out <= '0' & soda_cmd_word_S;
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
+ buf_bus_data_out <= '0' & super_burst_nr_S;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then
buf_bus_data_out <= calib_register_S;
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
buf_bus_data_out <= LEDregister_i;
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then
- buf_bus_data_out <= TEST_LINE_i;
+-- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
+-- buf_bus_data_out <= TEST_LINE_i;
end if;
end if;
end process THE_READ_REG_PROC;
-- output signals
+ LEDS_OUT <= LEDregister_i(3 downto 0);
+-- TEST_LINE <= TEST_LINE_i(15 downto 0);
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
-end architecture;
\ No newline at end of file
+end architecture;
signal tx_dlm_word : std_logic_vector(7 downto 0);
signal rx_dlm_word : std_logic_vector(7 downto 0);
- --SODA
- signal rst_S : std_logic;
- signal clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_cmd_strobe_S : std_logic := '0';
- signal SOS_S : std_logic := '0';
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal SOB_S : std_logic := '0';
- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
- signal dlm_valid_S : std_logic;
begin
---------------------------------------------------------------------------
THE_HUB : trb_net16_hub_base
generic map (
- HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
+ HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
IBUF_SECURE_MODE => c_YES,
MII_NUMBER => NUM_INTERFACES,
MII_IS_UPLINK => (0 => 1, others => 0),
COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
-- COMPILE_TIME => VERSION_NUMBER_TIME,
HARDWARE_VERSION => x"91003200",
- INIT_ENDPOINT_ID => x"0000",
- INIT_ADDRESS => x"F355",
+ INIT_ENDPOINT_ID => x"0003",
+ INIT_ADDRESS => x"F356",
USE_VAR_ENDPOINT_ID => c_YES,
BROADCAST_SPECIAL_ADDR => x"45",
CLOCK_FREQUENCY => CLOCK_FREQUENCY
\r
A_SODA_CLIENT : soda_client
port map(
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
+ SYSCLK => clk_sys_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
CLK_EN => '1',
--Internal Connection
RX_DLM_WORD_IN => rx_dlm_word,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
SODA_ACK_OUT => soda_ack,
- STAT => open
+ LEDS_OUT => soda_leds
);
BUS_READ_ENABLE_OUT(1) => sci1_read,
BUS_READ_ENABLE_OUT(2) => sci2_read,
BUS_READ_ENABLE_OUT(3) => soda_read,
-\r
+
BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
BUS_WRITE_ENABLE_OUT(1) => sci1_write,
BUS_WRITE_ENABLE_OUT(2) => sci2_write,
BUS_WRITE_ENABLE_OUT(3) => soda_write,
- \r
+
BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
- \r
+
BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
- \r
+
BUS_TIMEOUT_OUT(0) => open,
BUS_TIMEOUT_OUT(1) => open,
BUS_TIMEOUT_OUT(2) => open,
BUS_TIMEOUT_OUT(3) => open,
- \r
+
BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
- \r
+
BUS_DATAREADY_IN(0) => spimem_dataready_out,
BUS_DATAREADY_IN(1) => sci1_ack,
BUS_DATAREADY_IN(2) => sci2_ack,
BUS_DATAREADY_IN(3) => soda_ack,
- \r
+
BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
BUS_WRITE_ACK_IN(1) => sci1_ack,
BUS_WRITE_ACK_IN(2) => sci2_ack,
BUS_WRITE_ACK_IN(3) => soda_ack,
- \r
+
BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
BUS_NO_MORE_DATA_IN(1) => '0',
BUS_NO_MORE_DATA_IN(2) => '0',
BUS_NO_MORE_DATA_IN(3) => '0',
- \r
+
BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
BUS_UNKNOWN_ADDR_IN(1) => '0',
BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
-- The Soda Central
---------------------------------------------------------------------------
-- tx_dlm_i <= '0';
--- tx_dlm_word <= x"00";\r
+-- tx_dlm_word <= x"00";
THE_SOB_SOURCE : soda_start_of_burst_faker
port map(
SYSCLK => clk_sys_i,
SODA_ADDR_IN => soda_addr,
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
- LEDS_OUT => soda_leds,
- TEST_LINE => TEST_LINE(15 downto 0),\r
- STAT => open
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => soda_leds
);
-end trb3_periph_sodasource_arch;
\ No newline at end of file
+end trb3_periph_sodasource_arch;
jspc29 / soda.git / commitdiff