*** empty log message ***

diff --git a/design/initialization_RAM.vhd b/design/initialization_RAM.vhd
index 39f9fb0ba6b2d912d2dd50561993a5b1f520180e..bd6c8bd8b8d56b7b3f54789de09d7f9ecb32fafe 100644 (file)
--- a/design/initialization_RAM.vhd
+++ b/design/initialization_RAM.vhd
@@ -284,7 +284,8 @@ architecture Structure of initialization_RAM is
     attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4";--REGISTER_1    
                                                            --<REGISTER_1
     attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120";
-    attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0            
+    attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0
+                                                                                                                                                     
     attribute INITVAL_05 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114"; 
     attribute INITVAL_04 of initialization_RAM_0_0_0 : label is "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 1D 19 15 11 
    
@@ -357,54 +358,53 @@ begin
         INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
         INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
        
-
 -------------------------------------------------------------------------------
--- FEE CALIBRATION (1 LONG): START REGISTER 1 
+-- FEE CALIBRATION (1 LONG)
 -------------------------------------------------------------------------------
        INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
-       INITVAL_13=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4", 
+   --AFTER MODE CHANGED
+       INITVAL_13=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",
+                                                             --<END FIRST PART 
        INITVAL_12=> "0x0009900084000990006400099000440009900024000BD00184000BD00164000BD00144000BD00124",
-                                                             --> CHANGE THE MODE
+                                                             
        INITVAL_11=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1 
 
 -------------------------------------------------------------------------------
--- FEE CALIBRATION (1 SHORT): 
+-- FEE CALIBRATION (1 SHORT)
 -------------------------------------------------------------------------------
-        INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
-
+        INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",                            
+  --AFTER MODE CHANGED
         INITVAL_0F=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1  
---> CHANGE THE MODE
         INITVAL_0E=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1 
                                                 
 -------------------------------------------------------------------------------
--- FEE INIT:1 LONG MB
+-- FEE INIT: 1 LONG MB
 -------------------------------------------------------------------------------
 
-        INITVAL_0D=> "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018", 
-        INITVAL_0C=> "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 
-     -- INITVAL_0D=> "0x000000000000000000000000000000000100011400000000340000000030000000001C0000000018", 
-     -- INITVAL_0C=> "0x00000000140000000010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 
-
-       INITVAL_0B=> "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC",--REGISTER_3
+       INITVAL_0D=> "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018", -- GLOBAL DISABLE in CPLD
+       INITVAL_0C=> "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 
+     
+       INITVAL_0B=> "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC",
                                                             --<REGISTER_3
-       INITVAL_0A=> "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128", 
+       INITVAL_0A=> "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128",
+                                                            
        INITVAL_09=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
-       INITVAL_08=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",--REGISTER_1    
+       INITVAL_08=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",    
                                                             --<REGISTER_1
        INITVAL_07=> "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120",
        INITVAL_06=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0
-                                                                                                         --
+
 ------------------------------------------------------------------------------
--- 1 SHORT MB
+-- FEE INIT: 1 SHORT MB (CHANGE REGISTER_2 TO CHOOSE WHICH CHANNEL CALIBRATE)
 -------------------------------------------------------------------------------
        INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114", 
-       INITVAL_04=> "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010",
---         INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114", 
---         INITVAL_04=> "0x000610001C000610001800061000140006100010000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 1D 19 15 11 
-        INITVAL_03=> "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C",--REGISTER_3
-        INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
-        INITVAL_01=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1
-        INITVAL_00=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0(101_lastTDC_shortMb) 
+       INITVAL_04=> "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 1D 19 15 11
+       INITVAL_03=> "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C",--REGISTER_3
+       INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
+       --INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
+       --2 CAL TDC1 ONLY
+       INITVAL_01=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1
+       INITVAL_00=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0(101_lastTDC_shortMb) 
                      
         CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 

diff --git a/design/load_ROC1_tdc_setup.vhd b/design/load_ROC1_tdc_setup.vhd
index a9dee2062d9ea68eaf43a17fe63eeeec71b9f0e2..701bca94ba319d4db44e8c6c4b8d3d5f8199afa1 100644 (file)
--- a/design/load_ROC1_tdc_setup.vhd
+++ b/design/load_ROC1_tdc_setup.vhd
@@ -7,20 +7,15 @@
 --
 -- 20/11/2007 I added the configuration for chains (2 long MB, 2 short MB)
 --
---test 10/12
+-- MOTHERBOARD_TYPE_IN <= x"1" 1 SHORT MB
+-- MOTHERBOARD_TYPE_IN <= x"2" 1 LONG MB
 ------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.STD_LOGIC_ARITH.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
 use ieee.Numeric_STD.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
--- library UNISIM;
--- use UNISIM.VComponents.all;
 
-library IEEE;
-use IEEE.std_logic_1164.all;
 -- synopsys translate_off
 library ecp2m;
 use ecp2m.components.all;
@@ -44,7 +39,7 @@ entity load_ROC1_tdc_setup is
     A_AOD                         : out std_logic;
 
     TDC_SETTING_LOADED_OUT : out std_logic;
-    BUS_CHAIN_IN           : in  std_logic_vector(3 downto 0);
+    MOTHERBOARD_TYPE_IN           : in  std_logic_vector(3 downto 0);  
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM
 -------------------------------------------------------------------------------
@@ -109,7 +104,7 @@ architecture behaviour of load_ROC1_tdc_setup is
   signal reg_A_AOD, next_A_AOD                                       : std_logic;
   signal reg_TDC_SETTING_LOADED_OUT, next_TDC_SETTING_LOADED_OUT     : std_logic;
  -- signal offset_address                                              : std_logic;
-  signal bus_chain                                                   : std_logic_vector(3 downto 0);
+  signal motherboard_type_in_i                                         : std_logic_vector(3 downto 0);
   signal stop_counter_ram, counter_ram, offset_ram, temp_counter_ram : std_logic_vector(9 downto 0);
   signal calibration_stop_counter_ram_0, calibration_offset_ram        : std_logic_vector(9 downto 0);
   signal calibration_stop_counter_ram_1, calibration_stop_counter_ram: std_logic_vector(9 downto 0);
@@ -146,326 +141,11 @@ architecture behaviour of load_ROC1_tdc_setup is
 
 begin 
 
-
---   RAMB16_S18_CONFIGURATION_TDC_DATA : RAMB16_S18_S18
---   generic map (
--- -- The following generics are only necessary if you wish to
--- -- change the default behavior.
---       INIT_A       => X"00000",          -- Value of output RAM registers at startup
---       INIT_B       => X"00000",
---       SRVAL_A      => X"00000",          -- Ouput value upon SSR assertion
---       SRVAL_B      => X"00000",
---       WRITE_MODE_A => "WRITE_FIRST",    -- WRITE_FIRST, READ_FIRST or NO_CHANGE
---       WRITE_MODE_B => "WRITE_FIRST",
--- -- The following generic INIT_xx declarations are only necessary
--- -- if you wish to change the initial
--- -- contents of the RAM to anything other than all zero's.
-
--- -------------------------------------------------------------------------
--- -- 2 SHORT MOTHERBOARDs in chain 
--- -------------------------------------------------------------------------
--- ----A and B
---       --first MB: START REGISTER 0
---       INIT_00      => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"0")
---       --first MB: END REGISTER 0
-
---       --second MB: START REGISTER 0
---       INIT_01      => X"00170102001700E2001700C2001700A200170082001700620017004200170022", 
---       --second MB: END REGISTER 0
-
---       --first MB: START REGISTER 1
---       INIT_02      => X"00990105009900E5009900C5009900A500990085009900650099004500990025", 
---       --first MB: END REGISTER 1
-
---       --second MB: START REGISTER 1
---       INIT_03      => X"00990106009900E6009900C6009900A600990086009900660099004600990026", 
---       --second MB: END REGISTER 1
-
---       --first MB: START REGISTER 2
---       INIT_04      => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
--- --       INIT_04       => X"00010109000100E9000100C9000100A900010089000100690001004900010029", 
---       --first MB: END REGISTER 2
-
---       --second MB: START REGISTER 2
--- --      INIT_05      => X"00FF010A00FF00EA00FF00CA00FF00AA00FF008A00FF006A00FF004A00FF002A",
---       INIT_05        => X"0002010A000200EA000200CA000200AA0002008A0002006A0002004A0004002A", 
---        --second MB: END REGISTER 2
-
---       --first MB: START REGISTER 3 (all channels enable)
---       INIT_06      => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D", 
---       --first MB: END REGISTER 3
-
---       --second MB: START REGISTER 3 (I enable only tdc 1)
---       --INIT_07      => X"0000010E000000EE000000CE000000AE0000008E0000006E0000004E00FF002E", 
-
---       --all channel enable
---       INIT_07      => X"00FF010E00FF00EE00FF00CE00FF00AE00FF008E00FF006E00FF004E00FF002E", 
---       --second MB: END REGISTER 3
-
---       --first board: START DAQ REGISTER -- 1D 19 15 11
---      -- INIT_08    => X"0060001D00600019006000150060001100FF001D00FF001900FF001500FF0011",
---       INIT_08      => X"0010001D00100019001000150010001100FF001D00FF001900FF001500FF0011",
---       --first board: END DAQ REGISTER
-
---       --second board: START DAQ REGISTER  -- 1E 1A 16 12 
---      --INIT_09      => X"0060001E0060001A006000160060001200FF001E00FF001A00FF001600FF0012",
---         INIT_09     => X"0010001E0010001A001000160010001200FF001E00FF001A00FF001600FF0012",
--- --second board: END DAQ REGISTER
-      
---       --SET RESET REGISTER FOR GLOBAL DISABLE in CPLD
---       INIT_0A      => X"0000000000000000000000000000000000000000000000000010011600100115", --pointer(X"A4")
---       --END RESET REGISTER
--- -------------------------------------------------------------------------
--- -- end ROC file.
--- -------------------------------------------------------------------------
-
--- -------------------------------------------------------------------------
--- -- 1 SHORT MOTHERBOARD
--- -------------------------------------------------------------------------
---       --first MB: START REGISTER 0
---       INIT_0B      => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"B1")
---       --first MB: END REGISTER 0
-
---       --first MB: START REGISTER 1
---       INIT_0C      => X"00990105009900E5009900C5009900A500990085009900650099004500990025", 
---       --first MB: END REGISTER 1
-
---       --first MB: START REGISTER 2
---      -- INIT_0D      => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
--- --cal TDC1  INIT_0D      => X"00000109000000E9000000C9000000A900000089000000690000004900FF0029", 
--- --cal TDC1  INIT_0D=>  X"00050109000400E9000200C9000100A90004008900FF00690000004900000029", 
---       INIT_0D      =>  X"00010109002400E9004200C9008100A900100089000200690004004900800029", 
--- --first MB: END REGISTER 2
-      
---       --first MB: START REGISTER 3
---       --all channel enable
---       INIT_0E      => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D", 
---       --first MB: END REGISTER 3
-
---       --first board: START DAQ REGISTER 1D 19 15 11
---       --INIT_0F    => X"0060001D00600019006000150060001100FF001D00FF001900FF001500FF0011",
---       INIT_0F      => X"0010001D0010001900100015001000110010001D001000190010001500100011",
---    -- INIT_0F      => X"0045001D00450019004500150045001100FF001D00FF001900FF001500FF0011",
---       --first board: END DAQ REGISTER
-
---       --SET RESET REGISTER FOR GLOBAL DISABLE in CPLD
---       INIT_10    => X"0000000000000000000000000000000000000000000000000000000000100115", --pointer(X"101")
---       --END RESET REGISTER
--- -------------------------------------------------------------------------
--- -- end ROC file.
--- -------------------------------------------------------------------------
-
--- -------------------------------------------------------------------------
--- -- 1 LONG MOTHERBOARD
--- -------------------------------------------------------------------------
---   --START REGISTER 0 AND REGISTER 1
---       INIT_11      => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"110")
---                                                      --<
---       INIT_12      => X"0099008500990065009900450099002500170181001701610017014100170121", 
---                                                      --<
---       INIT_13      => X"0099018500990165009901450099012500990105009900E5009900C5009900A5",
-
---       --START REGISTER 2 AND REGISTER 3
---       INIT_14      => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
---                                                      --<
---       INIT_15      => X"00FF008D00FF006D00FF004D00FF002D00FF018900FF016900FF014900FF0129",
---                                                      --<
---       INIT_16      => X"00FF018D00FF016D00FF014D00FF012D00FF010D00FF00ED00FF00CD00FF00AD",
-
---       --DAQ REGISTER: 35 31 1D 19 15 11
---       --INIT_17    => X"006000150060001100FF003500FF003100FF001D00FF001900FF001500FF0011",
---       INIT_17      => X"001000150010001100FF003500FF003100FF001D00FF001900FF001500FF0011",
-      
---       INIT_18      => X"0000000000000000000000000010011500600035006000310060001D00600019", --pointer(X"19E")
--- ------------------------------------------------------------------------
--- -- end ROC file.
--- -------------------------------------------------------------------------
--- -------------------------------------------------------------------------
-
--- -------------------------------------------------------------------------
--- -- 2 long MOTHERBOARDs in chain 
--- ------------------------------------------------------------------------- 
---       --first AND second MB: START REGISTER 0
---       INIT_19      => X"00170101001700E1001700C1001700A100170081001700610017004100170021", 
---                                                      --<
---       INIT_1A      => X"0017008200170062001700420017002200170181001701610017014100170121", 
---                                                      --<
---       INIT_1B      => X"0017018200170162001701420017012200170102001700E2001700C2001700A2",
---       --first AND second  MB: END REGISTER 0
-
---       --first AND second MB: START REGISTER 1
---       INIT_1C      => X"00990105009900E5009900C5009900A500990085009900650099004500990025", 
---                                                      --<
---       INIT_1D      => X"0099008600990066009900460099002600990185009901650099014500990125",
-
---       INIT_1E      => X"0099018600990166009901460099012600990106009900E6009900C6009900A6", 
---       --first AND second  MB: END REGISTER 1
-      
---       --first AND second MB: START REGISTER 2
---       INIT_1F      => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
--- --        INIT_1F      => X"00100109001000E9001000C9001000A900100089001000690010004900100029", 
---                                                      --<
---       INIT_20      => X"00FF008A00FF006A00FF004A00FF002A00FF018900FF016900FF014900FF0129",
--- --       INIT_20      => X"0004008A0004006A0004004A0004002A00040189000401690004014900040129",
-
--- --      INIT_21    => X"00FF018A00FF016A00FF014A00FF012A00FF010A00FF00EA00FF00CA00FF00AA",
--- --ok    INIT_21    => X"000F018A000F016A000F014A000F012A000F010A000F00EA000F00CA000F00AA",
--- --no ok INIT_21    => X"000F018A000F016A000F014A000F012A00FF010A00FF00EA00FF00CA00FF00AA",
--- --ok    INIT_21    => X"00FF018A00FF016A00FF014A000F012A000F010A000F00EA000F00CA000F00AA",
---       INIT_21  => X"00FF018A00FF016A00FF014A00FF012A000F010A000F00EA000F00CA000F00AA",
--- --no ok   INIT_21  => X"00FF018A00FF016A00FF014A00FF012A00FF010A000F00EA000F00CA000F00AA",
--- --no ok   INIT_21    => X"00FF018A00FF016A00FF014A00FF012A000F010A00FF00EA000F00CA000F00AA",
-      
---       --first AND second MB: END REGISTER 2
-
---       --first AND second MB: START REGISTER 3
---       INIT_22      => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D", 
---                                                      --<
---       INIT_23      => X"00FF008E00FF006E00FF004E00FF002E00FF018D00FF016D00FF014D00FF012D",
-
---       INIT_24      => X"00FF018E00FF016E00FF014E00FF012E00FF010E00FF00EE00FF00CE00FF00AE", 
---       --first AND second MB: END REGISTER 3      
-
---       --first AND second MB: DAQ REGISTER: --36 32 1E 1A 16 12(second) 35 31 1D 19 15 11 (first board)
---       INIT_25      => X"001000150010001100FF003500FF003100FF001D00FF001900FF001500FF0011",
---                                                      --<
---       INIT_26      => X"00FF001E00FF001A00FF001600FF001200100035001000310010001D00100019",
---                                                      --<
---       INIT_27      => X"00100036001000320010001E0010001A001000160010001200FF003600FF0032",
-
---       INIT_28      => X"0000000000000000000000000000000000000000000000000010011600100115",
--- -------------------------------------------------------------------------
--- -- end ROC file.
--- -------------------------------------------------------------------------
-
-
--- -------------------------------------------------------------------------------
--- --CALIBRATION PARAMETERS CAL FILE
--- --!!!REMEMBER TO FIX THE GED BEFORE AND AFTER YOU LOAD THE CAL PARAMETERS!!!!!!
--- -- i CAN DO IT IN THE CODE!!!
--- -------------------------------------------------------------------------------      
-
--- -------------------------------------------------------------------------------
--- -- GDE registers for CAL file
--- -------------------------------------------------------------------------------
--- --I do this in the state machine!! this will never change
--- -------------------------------------------------------------------------
--- -- 1 SHORT MOTHERBOARD
--- -------------------------------------------------------------------------
---       --first MB: START REGISTER 1
---       INIT_29      => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025",
---     --  INIT_29        => X"00BA010500BB00E5002200C5000000A5000000850055006500AA004500BD0025",
---       --first MB: END REGISTER 1
-
---       --first MB: START REGISTER 1 AFTER CHANGED THE MODE
---       INIT_2A      => X"00990105009900E5009900C5009900A500990085009900650099004500990025", 
---       --first MB: END REGISTER 1
---       INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000100115",
--- -------------------------------------------------------------------------
--- -- 2 SHORT MOTHERBOARDs in chain 
--- -------------------------------------------------------------------------
---       --first MB: START REGISTER 1
---       INIT_2C      => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025", 
---       --first MB: END REGISTER 1
-
---       --second MB: START REGISTER 1
---       INIT_2D      => X"00BD010600BD00E600BD00C600BD00A600BD008600BD006600BD004600BD0026", 
---       --second MB: END REGISTER 1
-
---        --first MB: START REGISTER 1 AFTER CHANGED THE MODE
---       INIT_2E      => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
---       --first MB: END REGISTER 1
-
---       --second MB: START REGISTER 1
---       INIT_2F      => X"00990106009900E6009900C6009900A600990086009900660099004600990026",
---       --second MB: END REGISTER 1
---       INIT_30      => X"0000000000000000000000000000000000000000000000000010011600100115", 
--- -------------------------------------------------------------------------
--- -- 1 LONG MOTHERBOARD
--- -------------------------------------------------------------------------      
---       INIT_31      => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025", 
-                                                     
---       INIT_32      => X"0099008500990065009900450099002500BD018500BD016500BD014500BD0125",
---       -- AFTER CHANGED THE MODE
---       INIT_33      => X"0099018500990165009901450099012500990105009900E5009900C5009900A5", 
-                                                     
---       INIT_34      => X"0000000000000000000000000000000000000000000000000000000000100115",
--- -------------------------------------------------------------------------
--- -- 2 LONG MOTHERBOARDS
--- -------------------------------------------------------------------------
---        --first AND second MB: START REGISTER 1
---       INIT_35      => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025", 
---                                                      --<
---       INIT_36      => X"00BD008600BD006600BD004600BD002600BD018500BD016500BD014500BD0125",
-
---       INIT_37      => X"00BD018600BD016600BD014600BD012600BD010600BD00E600BD00C600BD00A6", 
---       --first AND second  MB: END REGISTER 1
--- -- AFTER CHANGED THE MODE
---        --first AND second MB: START REGISTER 1
---       INIT_38      => X"00990105009900E5009900C5009900A500990085009900650099004500990025", 
---                                                      --<
---       INIT_39      => X"0099008600990066009900460099002600990185009901650099014500990125",
-
---       INIT_3A      => X"0099018600990166009901460099012600990106009900E6009900C6009900A6", 
--- --first AND second  MB: END REGISTER 1
---       INIT_3B      => X"0000000000000000000000000000000000000000000000000010011600100115",
-      
---      -- INIT_29      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_2A      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_2B      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_2C      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_2D      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_2E      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_2F      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_30      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_31      => X"0000000000000000000000000000000000000000000000000000000000000000",
---     --  INIT_32      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_33      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_34      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_35      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_36      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_37      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_38      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_39      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_3A      => X"0000000000000000000000000000000000000000000000000000000000000000",
---      -- INIT_3B      => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INIT_3C      => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INIT_3D      => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INIT_3E      => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INIT_3F      => X"0000000000000000000000000000000000000000000000000000000000000000",
-
--- -- The next set of INITP_xx are for the parity bits
--- -- Address 0 to 255
---       INITP_00     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_01     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_02     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_03     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_04     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_05     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_06     => X"0000000000000000000000000000000000000000000000000000000000000000",
---       INITP_07     => X"0000000000000000000000000000000000000000000000000000000000000000")
-
---     port map (
---       DOA   => send_data,               -- Port A 16-bit Data Output
---       DOB   => RAM_DATA_OUT, --open,    -- Port B 16-bit Data Output
---       DOPA  => open,                    -- Port A 2-bit Parity Output
---       DOPB  => open,                    -- Port B 2-bit Parity Output
---       ADDRA => counter_ram,             -- counter_out,  -- Port A 10-bit Address Input
---       ADDRB => external_ram_address,--"0000000000",   -- Port B 10-bit Address Input
---       CLKA  => CLK,                     -- Port A Clock
---       CLKB  => CLK,                     -- Port B Clock
---       DIA   => (others => '0'),         -- Port A 16-bit Data Input
---       DIB   => external_ram_data,       -- Port B 16-bit Data Input
---       DIPA  => (others => '0'),         -- Port A 2-bit parity Input
---       DIPB  => (others => '0'),         -- Port-B 2-bit parity Input
---       ENA   => '1',                     -- Port A RAM Enable Input
---       ENB   => write_or_read_enable, --'0',  -- PortB RAM Enable Input
---       SSRA  => RESET,                   -- Port A Synchronous Set/Reset Input
---       SSRB  => RESET,                   -- Port B Synchronous Set/Reset Input
---       WEA   => '0',                     -- Port A Write Enable Input
---       WEB   => external_write_enable  --'0'  -- Port B Write Enable Input
---       );
--- -- End of RAMB16_S9_S9 instantiation
+ -------------------------------------------------------------------------------
+ --CALIBRATION PARAMETERS CAL FILE
+ --!!!REMEMBER TO FIX THE GED BEFORE AND AFTER YOU LOAD THE CAL PARAMETERS!!!!!!
+ -- i CAN DO IT IN THE CODE!!!
+ -------------------------------------------------------------------------------      
 
    external_ram_address  <= RAM_ADDRESS_IN;
    external_ram_data     <= RAM_DATA_IN;
@@ -475,21 +155,22 @@ begin
 
   RAM_configuration: initialization_RAM
     port map (
-        DataInA  => (others => '0'),--DataInA_i,
-        DataInB  => external_ram_data,--DataInB_i,
+        DataInA  => (others => '0'),
+        DataInB  => external_ram_data,
         AddressA => counter_ram(8 downto 0), --AddressA_i, --9 bits
-        AddressB => external_ram_address,--(others => '0'),--AddressB_i,
-        ClockA   => CLK,--ClockA_i,
-        ClockB   => CLK,--ClockB_i,
-        ClockEnA => '1',--ClockEnA_i,
-        ClockEnB => '1',--'0',--ClockEnB_i,
+        AddressB => external_ram_address,
+        ClockA   => CLK,
+        ClockB   => CLK,
+        ClockEnA => '1',
+        ClockEnB => '1',
         WrA      => '0',
         WrB      => external_write_enable,
-        ResetA   => '0',--ResetA_i,
-        ResetB   => '0',--ResetB_i,
-        QA       => send_data, -- RAM_DATA_OUT, -- Port A 16-bit Data Output
-        QB       => RAM_DATA_OUT --open-- Port B 16-bit Data Output
+        ResetA   => '0',
+        ResetB   => '0',
+        QA       => send_data,
+        QB       => RAM_DATA_OUT 
         );
+   
 -------------------------------------------------------------------------------
 --purpose: state machine synchronization
 -------------------------------------------------------------------------------  
@@ -515,8 +196,7 @@ begin
 A_DST <= reg_A_DST;
 A_AOD <= reg_A_AOD;  
 TDC_SETTING_LOADED_OUT <= reg_TDC_SETTING_LOADED_OUT;
---bus_chain <= BUS_CHAIN_IN;
-bus_chain <= x"1";
+motherboard_type_in_i <= MOTHERBOARD_TYPE_IN;
 
   DEBUG_REGISTER <= reg_debug_register;
 -------------------------------------------------------------------------------
@@ -528,7 +208,7 @@ bus_chain <= x"1";
            time_counter, CALIBRATION_STEP_TDC_SETUP,
            CALIBRATION_TRIGGER_TDC_SETUP, calibration_counter_0,
            counter_register_1, counter_delay,
-           bus_chain, control_register_0,
+           motherboard_type_in_i, control_register_0,
            cpld_register_data)
   begin
     next_A_DST <= '0';
@@ -693,7 +373,7 @@ bus_chain <= x"1";
         clear_time_counter <= '1';
         clear_calibration_counter_0 <= '1';
         if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
-           next_state <= calibration_state_0;--bus_chain <= x"1" 1 short MB in the bus
+           next_state <= calibration_state_0;--motherboard_type_in_i <= x"1" 1 short MB in the bus
          else
            next_state <= stop_state;
          end if;
@@ -811,14 +491,10 @@ bus_chain <= x"1";
         A_ADD(8 downto 0)           <= x"00" & '0';
         clear_calibration_counter_0 <= '1';
         up_control_register_0 <= '1';
---         if (bus_chain = x"2" or bus_chain = x"4") then  --2 short or 2 long in chain
---           next_state          <= calibration_state_0;  --repeat and write again
---         else
-          next_state          <= wait_calibration_state_6;
---         end if;
- ------------------------------------------------------------------------------
- -- 
- ------------------------------------------------------------------------------       
+        next_state          <= wait_calibration_state_6;
+------------------------------------------------------------------------------
+-- 
+------------------------------------------------------------------------------       
       when wait_calibration_state_6 =>  --wait till TSTW+GDE (1a01 08) mode line are fixed
         next_debug_register <= x"12";
         next_A_DST          <= '0';
@@ -1048,10 +724,8 @@ end process;
 --Here I decide where I have to stop to take data from RAM, depending which
 --kind of chain is connected to the bus
 --
---bus_chain <= x"1" 1 short MB in the bus
---bus_chain <= x"2" 2 short MBs in the same bus
---bus_chain <= x"3" 1 long MB in the bus
---bus_chain <= x"4" 2 long MBs in the same bus
+--motherboard_type_in_i <= x"1" short MB
+--motherboard_type_in_i <= x"2" long MB 
 -------------------------------------------------------------------------------
 process (CLK)
 begin
@@ -1105,35 +779,33 @@ begin
 -------------------------------------------------------------------------------
 --CALIBRATION
 -------------------------------------------------------------------------------      
-    elsif process_trigger_type = x"C" then 
-      if bus_chain = x"1" then    --1 short MB is configured
-        calibration_stop_counter_ram_0 <=  "00" & x"EF";-- stop wrting the first register,
-                                                        -- before change the mode line
-                                           
-        calibration_offset_ram         <= "00" & x"DE";--x"E0";
-        calibration_stop_counter_ram_1 <=  "01" & x"01";  --finish calibration 101
+    elsif process_trigger_type = x"C" then
+      if motherboard_type_in_i = x"1" then  --1 short MB is configured
+        calibration_stop_counter_ram_0 <= "00" & x"EF";  -- stop wrting the first register
+                                                         -- before change the mode line
+        calibration_offset_ram         <= "00" & x"DE"; 
+        calibration_stop_counter_ram_1 <= "01" & x"01";  --finish calibration 101
+
+      elsif motherboard_type_in_i = x"2" then  --1 long MB is configured    
+        calibration_stop_counter_ram_0 <= "01" & x"27";  
+        calibration_offset_ram         <= "01" & x"0E";  
+        calibration_stop_counter_ram_1 <= "01" & x"41";
+      end if;
 
---       elsif bus_chain = x"2" then --1 long MB is configured    
---          calibration_stop_counter_ram_0 <= "1011011111";--0x2DF
---          calibration_offset_ram       <= "1010111110";--0x2BE
---          calibration_stop_counter_ram_1 <= "1100000011";--0x303
-       end if;
-        
 -------------------------------------------------------------------------------
 --BEGRUN TRIGGER
 -------------------------------------------------------------------------------
-    elsif process_trigger_type = x"B" then 
-      if bus_chain = x"1" then    --1 short MB is configured
-        stop_counter_ram             <= "00" & x"51"; --"0100000001";  --x"101"
-        offset_ram                   <= "00" & x"00";
+    elsif process_trigger_type = x"B" then
+      if motherboard_type_in_i = x"1" then  --1 short MB is configured
+        stop_counter_ram <= "00" & x"51";  --"0100000001";  --x"101"
+        offset_ram       <= "00" & x"00";
 
---       elsif bus_chain = x"2" then --1 long MB is configured
---         stop_counter_ram             <= "00" & x"DA";--"0110001001";  --x"189"
---         offset_ram                   <= "00" & x"60";--"0100010000";  --x"110"  
+      elsif motherboard_type_in_i = x"2" then  --1 long MB is configured
+        stop_counter_ram <= "00" & x"D9";  
+        offset_ram       <= "00" & x"60";  
       end if;
     end if;
   end if;
---end if;
 end process;
 
 -------------------------------------------------------------------------------
@@ -1154,7 +826,6 @@ begin
     end if;
   end if;
 end process;
---counter_ram <= temp_counter_ram + offset_ram;
 
 counter_ram <= (temp_counter_ram + offset_ram) when process_trigger_type <= x"B" else (temp_counter_ram + calibration_offset_ram);
 

diff --git a/design/mdc_addon_daq_bus_0.vhd b/design/mdc_addon_daq_bus_0.vhd
index d2d88ec3890f45a5d85f78354f43129e2ec7df73..10eeeeacaa1beea8a43047d5bff233a6f2c782f8 100644 (file)
--- a/design/mdc_addon_daq_bus_0.vhd
+++ b/design/mdc_addon_daq_bus_0.vhd
@@ -74,7 +74,7 @@ entity mdc_addon_daq_bus_0 is
     ROC1_WRITTEN_OUT             : out std_logic;
     --BUS_NUMBER_IN                : in  std_logic_vector(3 downto 0);
     DIRECTION_DATA_LINE_IN       : out  std_logic_vector(3 downto 0);
-    BUS_CHAIN_IN                 : in  std_logic_vector(3 downto 0);
+    MOTHERBOARD_TYPE_IN                 : in  std_logic_vector(3 downto 0);
 -------------------------------------------------------------------------------
 -- TRB INTERFACE
 -------------------------------------------------------------------------------
@@ -181,7 +181,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is
       A_WRM : out std_logic;            -- TDC working mode
 
       TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);  -- I use 4 bit for trigger
-      BUS_CHAIN_IN    : in std_logic_vector(3 downto 0);
+      MOTHERBOARD_TYPE_IN    : in std_logic_vector(3 downto 0);
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM
 -------------------------------------------------------------------------------
@@ -308,7 +308,7 @@ begin  --behavioral
       A_TOK            => a_tok_i,
       A_WRM            => a_wrm_i,
       TRIGGER_TYPE_IN  => init_trigger_handle_tld_i,  --trigger_type_out_i,
-      BUS_CHAIN_IN     => BUS_CHAIN_IN,
+      MOTHERBOARD_TYPE_IN     => MOTHERBOARD_TYPE_IN,
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM
 -------------------------------------------------------------------------------
@@ -370,7 +370,7 @@ begin  --behavioral
       TOKEN_IN              => token_back_out_i,
       INIT_TDC_READOUT_IN   => init_tdc_readout_i,
 
-      BUS_NUMBER_IN         => open, --BUS_NUMBER_IN,
+      BUS_NUMBER_IN         => x"1", --BUS_NUMBER_IN,
       -- INIT_TRB_INTERFACE_IN => init_trb_interface_i,
       TOKEN_TO_TRB_OUT      => token_to_trb_i,
       REINIT_ROC1_IN        => reinit_roc1_i,

diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd
index 555689491f4ba71bd17e3e8c9a17f10f0677945b..c66aa23949065651da80bfca7a81bba5d17e1bc4 100644 (file)
--- a/design/mdc_oepb_pack.vhd
+++ b/design/mdc_oepb_pack.vhd
@@ -44,14 +44,15 @@ component mdc_addon_daq_bus_0
       D                            : out   std_logic_vector(6 downto 0);
       A_RDO_OUT                    : out   std_logic;
       ROC1_WRITTEN_OUT             : out   std_logic;
-      BUS_NUMBER_IN                : in    std_logic_vector(3 downto 0);
-      BUS_CHAIN_IN                 : in    std_logic_vector(3 downto 0);
+      --BUS_NUMBER_IN                : in    std_logic_vector(3 downto 0);
+      DIRECTION_DATA_LINE_IN       : out   std_logic_vector(3 downto 0);
+      MOTHERBOARD_TYPE_IN          : in    std_logic_vector(3 downto 0);
       ACKNOWLEDGE_TRB_INTERFACE_IN : in    std_logic_vector(3 downto 0);
       INIT_TRB_INTERFACE_OUT       : out   std_logic;
       DATA_OUT                     : out   std_logic_vector(25 downto 0);
       READ_FIFO_IN                 : in    std_logic;
       DEBUG_REGISTER_TRB_INTERFACE : in    std_logic_vector(3 downto 0);
-      RAM_ADDRESS_IN               : in    std_logic_vector(9 downto 0);
+      RAM_ADDRESS_IN               : in    std_logic_vector(8 downto 0);
       RAM_DATA_IN                  : in    std_logic_vector(15 downto 0);
       RAM_DATA_OUT                 : out   std_logic_vector(15 downto 0);
       RAM_READ_ENABLE_IN           : in    std_logic;
@@ -321,5 +322,12 @@ component mdc_addon_daq_bus_0
       );
   end component;
 
+component edge_to_pulse
+  port (
+    CLOCK         : in  std_logic;
+    ENABLE_CLK_IN : in  std_logic;
+    SIGNAL_IN     : in  std_logic;
+    PULSE_OUT     : out std_logic);
+end component;
 
-end package mdc_oepb_pack;
\ No newline at end of file
+end package mdc_oepb_pack;

diff --git a/design/trigger_begrun_state.vhd b/design/trigger_begrun_state.vhd
index 6f6def9bc48ad154112bd29e9f49b6bdea41fc90..055d55f02438d745585c81c67225baaa2692faca 100644 (file)
--- a/design/trigger_begrun_state.vhd
+++ b/design/trigger_begrun_state.vhd
@@ -3,11 +3,6 @@ use IEEE.STD_LOGIC_1164.all;
 use IEEE.STD_LOGIC_ARITH.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
--- library UNISIM;
--- use UNISIM.VComponents.all;
-
 entity trigger_begrun_state is
   port(
     CLK      : in  std_logic;         --for testing
@@ -33,7 +28,7 @@ entity trigger_begrun_state is
     RAM_WRITE_ENABLE_IN   : in std_logic; 
 
     BEGRUN_TRIGGER : in std_logic;        --test the sub entity it starts "load_ROC1_configuration_data"
-    BUS_CHAIN_IN        : in  std_logic_vector(3 downto 0);
+    MOTHERBOARD_TYPE_IN        : in  std_logic_vector(3 downto 0);
     CALIBRATION_TRIGGER : in std_logic;
     RESET        : in std_logic;
     ROC1_WRITTEN : out std_logic;
@@ -118,7 +113,7 @@ architecture Behavioral of trigger_begrun_state is
        A_DST                         : out std_logic;
        A_AOD                         : out std_logic;  --address or data
        TDC_SETTING_LOADED_OUT        : out std_logic;
-       BUS_CHAIN_IN                  : in  std_logic_vector(3 downto 0);
+       MOTHERBOARD_TYPE_IN                  : in  std_logic_vector(3 downto 0);
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM 
 -------------------------------------------------------------------------------
@@ -169,7 +164,7 @@ begin
        A_AOD                    => A_AOD,
 
        TDC_SETTING_LOADED_OUT   => tdc_setting_loaded_out_i,
-       BUS_CHAIN_IN             => x"1",--BUS_CHAIN_IN,   
+       MOTHERBOARD_TYPE_IN      => MOTHERBOARD_TYPE_IN,   
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM 
 -------------------------------------------------------------------------------

diff --git a/design/trigger_distributor.vhd b/design/trigger_distributor.vhd
index ef48f9043e02b13fbdc8d8452d43f01f6e272ad1..20427984abb7b6d7ec7787f9b30b899c6ce02903 100644 (file)
--- a/design/trigger_distributor.vhd
+++ b/design/trigger_distributor.vhd
@@ -105,7 +105,7 @@ begin  -- behavioral
   A_RDO_PULSE : edge_to_pulse
     port map (
       CLOCK              => CLK,
-      ENABLE_CLK_IN    => '1',
+      ENABLE_CLK_IN      => '1',
       SIGNAL_IN          => A_RDO_IN,
       PULSE_OUT          => pulse_a_rdo_in);
 
@@ -192,7 +192,7 @@ begin  -- behavioral
 
     case current_state is
 
-      when idle_state  =>
+      when idle_state                        =>
         next_debug_register       <= x"1";
         next_LED_CNT_1_OUT        <= '1';
         next_LED_CNT_2_OUT        <= '1';
@@ -204,15 +204,15 @@ begin  -- behavioral
         reset_calibration_counter <= '0';
         if (pulse_begin_run_trigger = '1') then
           next_state              <= begrun_trigger_state;
-        elsif (reg_trigger_in = '1' and internal_calibration_trigger = '0') then
-         -- next_state              <= normal_trigger_state;
-           next_state <= calibration_state;
-        elsif (reg_trigger_in = '1' and internal_calibration_trigger = '1') then
-          next_state <= calibration_state;
+        elsif (reg_trigger_in = '1') then
+          if (register_trigger_condition(3 downto 0) = x"C") then
+            next_state            <= calibration_state;
+          else
+            next_state            <= normal_trigger_state;
+          end if;
         else
           next_state              <= idle_state;
         end if;
-        
 -------------------------------------------------------------------------------
 --NORMAL TRIGGER
 -------------------------------------------------------------------------------

diff --git a/design/trigger_handle_tld.vhd b/design/trigger_handle_tld.vhd
index a37193945b502191d48da4a580405ef891ead0b9..77923b63e678d9be0aaf6235791e815517849393 100644 (file)
--- a/design/trigger_handle_tld.vhd
+++ b/design/trigger_handle_tld.vhd
@@ -3,11 +3,6 @@ use IEEE.STD_LOGIC_1164.all;
 use IEEE.STD_LOGIC_ARITH.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
 
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
--- library UNISIM;
--- use UNISIM.VComponents.all;
-
 entity trigger_handle_tld is
   port(
     CLK   : in  std_logic;                     --for testing
@@ -35,7 +30,7 @@ entity trigger_handle_tld is
     A_WRM : out std_logic;              -- TDC working mode
 
     TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);  -- I use 4 bit for trigger
-    BUS_CHAIN_IN    : in std_logic_vector(3 downto 0);
+    MOTHERBOARD_TYPE_IN    : in std_logic_vector(3 downto 0);
     
 -------------------------------------------------------------------------------
 -- SIGNALS for RAM 
@@ -110,7 +105,7 @@ architecture behavioral of trigger_handle_tld is
       RAM_WRITE_ENABLE_IN   : in std_logic; 
       
       BEGRUN_TRIGGER      : in  std_logic;  --test the sub entity it starts "load_ROC1_configuration_data"
-      BUS_CHAIN_IN        : in  std_logic_vector(3 downto 0);
+      MOTHERBOARD_TYPE_IN        : in  std_logic_vector(3 downto 0);
       CALIBRATION_TRIGGER : in  std_logic;
       RESET               : in  std_logic;
       ROC1_WRITTEN        : out std_logic;
@@ -203,7 +198,7 @@ begin  -- behavioral
       RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN,
 
       BEGRUN_TRIGGER => begrun_trigger_i,
-      BUS_CHAIN_IN   => BUS_CHAIN_IN,
+      MOTHERBOARD_TYPE_IN => MOTHERBOARD_TYPE_IN,
       CALIBRATION_TRIGGER => reg_calibration_trigger,
       RESET          => reset_i,
       ROC1_WRITTEN   => roc1_written_i,