increase speed of fast slow control to 5 MHz

diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd
index 958c2c7b88b378329f33f18ffd5530ebd1d766b8..18e23036d9a1afdcf57f2300ee86e21a13edd6c7 100644 (file)
--- a/mupix/Mupix8/sources/MupixBoard.vhd
+++ b/mupix/Mupix8/sources/MupixBoard.vhd
@@ -170,7 +170,7 @@ architecture Behavioral of MupixBoard8 is
   end component PixelControl;
 
   constant fpga_clk_speed      : integer := 1e8;  -- 100 MHz
-  constant mupix_spi_clk_speed : integer := 4e5;  -- 400 kHz
+  constant mupix_spi_clk_speed : integer := 5e6;  -- 5 MHz
   constant board_spi_clk_speed : integer := 5e4;  -- 50 kHz
   signal mupixslctrl_i         : MupixSlowControl;
 

diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd
index a5b67404a73977c15274687639afe1cef0a09cbe..288e59e22cc6adb2b6e116555f4b64c25c32e71d 100644 (file)
--- a/mupix/Mupix8/trb3_periph.vhd
+++ b/mupix/Mupix8/trb3_periph.vhd
@@ -117,7 +117,7 @@ end entity;
 architecture trb3_periph_arch of trb3_periph is
 
   constant c_clock_speed    : clk_speed_t := c_40MHz;  -- clock speed for data taking
-  constant c_linksimulation : integer     := c_YES;  -- built the link simulation part
+  constant c_linksimulation : integer     := c_No;  -- built the link simulation part
                                         -- only use clock speed = 40
                                         -- MHz with this option