add additional optional trigger outputs

diff --git a/releases/tdc_v2.3/trb3_periph_padiwa.vhd b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
index 090036afc3142b5e0922d649ebaef61e7778ec60..ed02b6edfd664455be14f89aba3e86ee0eb67335 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_padiwa.vhd
+++ b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
@@ -40,7 +40,8 @@ entity trb3_periph_padiwa is
 
     --Connections
 --     SPARE_LINE : inout std_logic_vector(3 downto 0);
-    INP        : in    std_logic_vector(63 downto 0);
+    INP               : in    std_logic_vector(PHYSICAL_INPUTS-1 downto 0);
+    ADDON_TRIGGER_OUT : out   std_logic_vector(USE_ADDON_TRIGGER_OUT*TRIG_GEN_OUTPUT_NUM-1 downto 0);
 
     --Flash ROM & Reboot
     FLASH_CLK  : out std_logic;
@@ -50,10 +51,10 @@ entity trb3_periph_padiwa is
     PROGRAMN   : out std_logic;         --reboot FPGA
 
     --DAC
-    OUT_SDO    : out   std_logic_vector(4 downto 1);
-    IN_SDI     : in    std_logic_vector(4 downto 1);
-    OUT_SCK    : out   std_logic_vector(4 downto 1);
-    OUT_CS     : out   std_logic_vector(4 downto 1);
+    OUT_SDO    : out   std_logic_vector(4-USE_ADDON_TRIGGER_OUT downto 1);
+    IN_SDI     : in    std_logic_vector(4-USE_ADDON_TRIGGER_OUT downto 1);
+    OUT_SCK    : out   std_logic_vector(4-USE_ADDON_TRIGGER_OUT downto 1);
+    OUT_CS     : out   std_logic_vector(4-USE_ADDON_TRIGGER_OUT downto 1);
     --Misc
     TEMPSENS   : inout std_logic;       --Temperature Sensor
     CODE_LINE  : in    std_logic_vector(1 downto 0);
@@ -131,17 +132,17 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
   signal feature_outputs_i : std_logic_vector(15 downto 0);
   signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0); 
   signal uart_rx, uart_tx, debug_rx, debug_tx         : std_logic;
-  signal trig_gen_out_i                               : std_logic_vector(3 downto 0);
+  signal trig_gen_out_i                               : std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);
   signal sed_error_i                                  : std_logic;
   signal serdes_i          : std_logic_vector(3 downto 0);
   attribute nopad : string;
   attribute nopad of  serdes_i : signal is "true";  
   
-  signal triggerlogic_out : std_logic_vector(7 downto 0);
-  signal triggerlogic_in  : std_logic_vector(28 downto 1);
+  -- signal triggerlogic_out : std_logic_vector(7 downto 0);
+  -- signal triggerlogic_in  : std_logic_vector(28 downto 1);
 
   --TDC
-  signal hit_in_i         : std_logic_vector(64 downto 1);
+  signal hit_in_i         : std_logic_vector(PHYSICAL_INPUTS downto 1);
   signal logic_analyser_i : std_logic_vector(15 downto 0);
 
 
@@ -349,9 +350,9 @@ begin
       DEBUG_TX_OUT  => debug_tx,
 
       --Trigger & Monitor 
-      MONITOR_INPUTS(51 downto 0) => hit_in_i(52 downto 1),
-      MONITOR_INPUTS(55 downto 52) => trig_gen_out_i,
-      TRIG_GEN_INPUTS  => hit_in_i(52 downto 1),
+      MONITOR_INPUTS(47 downto 0) => hit_in_i(PHYSICAL_INPUTS downto 1),
+      MONITOR_INPUTS(MONITOR_INPUT_NUM-1 downto PHYSICAL_INPUTS) => trig_gen_out_i,
+      TRIG_GEN_INPUTS  => hit_in_i(PHYSICAL_INPUTS downto 1),
       TRIG_GEN_OUTPUTS => trig_gen_out_i,
       LCD_OUT => lcd_out,
       --SED
@@ -384,8 +385,9 @@ begin
 --     INPUT  => triggerlogic_in,
 --     OUTPUT => triggerlogic_out(7 downto 0)
 --     );
-  FPGA5_COMM(10 downto 7) <= trig_gen_out_i;-- or triggerlogic_out(3 downto 0);
-
+  FPGA5_COMM(10 downto 7) <= trig_gen_out_i(3 downto 0);-- or triggerlogic_out(3 downto 0);
+  ADDON_TRIGGER_OUT(USE_ADDON_TRIGGER_OUT*TRIG_GEN_OUTPUT_NUM-1 downto 0) <= trig_gen_out_i(USE_ADDON_TRIGGER_OUT*TRIG_GEN_OUTPUT_NUM-1 downto 0);
+  
 --   triggerlogic_in <= hit_in_i(28 downto 1) when rising_edge(clk_100_i);
   --FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
 bustrigger_tx.ack <= '0';
@@ -415,10 +417,10 @@ bustrigger_tx.nack <= '0';
   feature_outputs_i(14) <= debug_rx;
   feature_outputs_i(15) <= debug_tx; 
 
-  OUT_CS   <= spi_cs(3 downto 0);
-  OUT_SCK  <= spi_clk(3 downto 0);
-  OUT_SDO  <= spi_mosi(3 downto 0);
-  spi_miso(3 downto 0) <= IN_SDI;
+  OUT_CS   <= spi_cs  (3-USE_ADDON_TRIGGER_OUT downto 0);
+  OUT_SCK  <= spi_clk (3-USE_ADDON_TRIGGER_OUT downto 0);
+  OUT_SDO  <= spi_mosi(3-USE_ADDON_TRIGGER_OUT downto 0);
+  spi_miso(3-USE_ADDON_TRIGGER_OUT downto 0) <= IN_SDI;
   
 ---------------------------------------------------------------------------
 -- LED
@@ -432,7 +434,7 @@ bustrigger_tx.nack <= '0';
 -- Test Connector
 ---------------------------------------------------------------------------    
 --  TEST_LINE(15 downto 0) <= (others => '0');
-  TEST_LINE(7 downto 0) <= triggerlogic_out;
+  -- TEST_LINE(7 downto 0) <= triggerlogic_out;
 
 ---------------------------------------------------------------------------
 -- Test Circuits
@@ -478,7 +480,7 @@ bustrigger_tx.nack <= '0';
 
   -- For ToT Measurements
   gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate
-    Gen_Hit_In_Signals : for i in 1 to 32 generate
+    Gen_Hit_In_Signals : for i in 1 to PHYSICAL_INPUTS generate
       hit_in_i(i*2-1) <= INP(i-1);
       hit_in_i(i*2)   <= not INP(i-1);
 --       input_i(i)      <= INP(i-1);
@@ -486,7 +488,7 @@ bustrigger_tx.nack <= '0';
   end generate;
 
   gen_double_padiwa_fast : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 1 generate
-    Gen_Hit_Fast_Signals : for i in 1 to 32 generate
+    Gen_Hit_Fast_Signals : for i in 1 to PHYSICAL_INPUTS generate
       hit_in_i(i*2-1) <= INP(i*2-2);
       hit_in_i(i*2)   <= not INP(i*2-2);
 --       input_i(i)      <= INP(i*2-2);