signal start : std_logic;
signal chipselect_reg : std_logic_vector(15 downto 0) := x"0001";
signal clear_reg : std_logic_vector(15 downto 0) := x"0000";
+ signal invert_reg : std_logic;
signal spi_cs : std_logic_vector(15 downto 0);
signal spi_sck : std_logic;
BUS_ACK_OUT <= '1';
if BUS_ADDR_IN(4) = '0' then
ram(addr) <= BUS_DATA_IN;
- elsif BUS_ADDR_IN(1) = '1' then
+ elsif BUS_ADDR_IN(2) = '1' then
clear_reg <= BUS_DATA_IN(15 downto 0);
+ elsif BUS_ADDR_IN(3) = '1' then
+ invert_reg <= BUS_DATA_IN(0);
elsif BUS_ADDR_IN(0) = '1' then
ctrl_reg <= BUS_DATA_IN;
start <= '1';
- else --if BUS_ADDR_IN(0) = '0' then
+ else --if BUS_ADDR_IN(0) = '0' then
chipselect_reg <= BUS_DATA_IN(15 downto 0);
end if;
else
BUS_DATA_OUT <= ram(addr);
elsif BUS_ADDR_IN(0) = '1' then
BUS_DATA_OUT <= ctrl_reg;
- elsif BUS_ADDR_IN(1) = '1' then
+ elsif BUS_ADDR_IN(2) = '1' then
BUS_DATA_OUT(15 downto 0) <= clear_reg;
BUS_DATA_OUT(31 downto 16) <= x"0000";
+ elsif BUS_ADDR_IN(3) = '1' then
+ BUS_DATA_OUT(0) <= invert_reg;
+ BUS_DATA_OUT(31 downto 1) <= (others => '0');
elsif BUS_ADDR_IN(1) = '1' then
BUS_DATA_OUT <= readback;
- else --if BUS_ADDR_IN(1) = '0' then
+ else --if BUS_ADDR_IN(1) = '0' then
BUS_DATA_OUT(15 downto 0) <= chipselect_reg;
BUS_DATA_OUT(31 downto 16) <= x"0000";
end if;
--- Outputs
- SPI_CS_OUT <= spi_cs;
- SPI_SCK_OUT <= spi_sck;
- SPI_SDO_OUT <= spi_sd;
+-- Outputs
+ Invert : process(invert_reg)
+ begin
+ if invert_reg = '1' then
+ SPI_CS_OUT <= not spi_cs;
+ SPI_SCK_OUT <= not spi_sck;
+ SPI_SDO_OUT <= not spi_sd;
+ else
+ SPI_CS_OUT <= spi_cs;
+ SPI_SCK_OUT <= spi_sck;
+ SPI_SDO_OUT <= spi_sd;
+ end if;
+ end process Invert;
SPI_CLR_OUT <= clear_reg;