type ram_addr_t is array (CHANNELS - 1 downto 0) of std_logic_vector(8 downto 0);
type ram_data_t is array (CHANNELS - 1 downto 0) of std_logic_vector(31 downto 0);
- type ram_counter_t is array (CHANNELS - 1 downto 0) of unsigned(8 downto 0);
+ type ram_counter_t is array (CHANNELS - 1 downto 0) of unsigned(2 downto 0);
signal ram_addr_adc, ram_addr_sys : ram_addr_t := (others => (others => '0'));
signal ram_data_adc, ram_data_sys : ram_data_t := (others => (others => '0'));
signal ram_counter : ram_counter_t := (others => (others => '0'));
type state_t is (IDLE, INTEGRATE, WRITE1, WRITE2, WRITE3, WRITE4, FINISH, WAIT_BSY);
signal state : state_t := IDLE;
- signal ram_counter : unsigned(8 downto 0) := (others => '0');
+ signal ram_counter : unsigned(2 downto 0) := (others => '0');
begin
-- input ADC data interpreted as unsigned
input <= unsigned(ADC_DATA);