edited compile script for cbmtof design

diff --git a/cbmtof/cbmtof.ldf b/cbmtof/cbmtof.ldf
deleted file mode 100644 (file)
index a6d33e7..0000000
--- a/cbmtof/cbmtof.ldf
+++ /dev/null
@@ -1,309 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="cbmtof" device="LFE3-150EA-8FN672C" default_implementation="cbmtof">
-    <Options/>
-    <Implementation title="cbmtof" dir="cbmtof" description="cbmtof" default_strategy="Strategy1">
-        <Options/>
-        <Options/>
-        <Source name="../version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3_periph_padiwa.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Adder_304.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/bit_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/BusHandler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Channel_200.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Channel.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Encoder_304_Bit.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/fallingEdgeDetect.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/FIFO_36x128_OutReg_Counter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/LogicAnalyser.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Readout.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Reference_Channel_200.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/Reference_Channel.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/risingEdgeDetect.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/ROM_encoder_3.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/ROM4_Encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/ShiftRegisterSISO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/TDC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/trb3_periph.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../tdc_releases/tdc_v1.3/up_counter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../workdir/cbmtof.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="Strategy1.sty"/>
-</BaliProject>

diff --git a/cbmtof/cbmtof.prj b/cbmtof/cbmtof.prj
index bbe2ed076dcf7a5f6db639fca3685f833cc3c455..8c3e0d99892fa58e881fbfbf3a3a3a014ac797b3 100644 (file)
--- a/cbmtof/cbmtof.prj
+++ b/cbmtof/cbmtof.prj
@@ -52,11 +52,11 @@ impl -active "workdir"
 #add_file options
 
 add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "currentRelease/tdc_version.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+add_file -vhdl -lib work "../base/trb3_components.vhd"
 
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
@@ -142,7 +142,7 @@ add_file -vhdl -lib work  "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
 
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
@@ -157,28 +157,32 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.v
 #Change path to tdc release also in compile script!
 ###############
 
-#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd"
-add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd"
-add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd"
-add_file -vhdl -lib "work" "currentRelease/Channel.vhd"
-add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd"
-add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd"
-add_file -vhdl -lib "work" "currentRelease/Readout.vhd"
-add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib "work" "currentRelease/TDC.vhd"
-add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd"
-add_file -vhdl -lib "work" "currentRelease/up_counter.vhd"
-add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
-add_file -vhdl -lib "work" "../base/code/input_statistics.vhd"
-add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
-
-
-add_file -vhdl -lib "work" "cbmtof.vhd"
+#add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/Readout.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+
+
+add_file -vhdl -lib work "cbmtof.vhd"
 

diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd
index 9e76f795f8fd49d2748239e79cb458ff0cd4de16..c348716fd4bf18074463899b54297e764dd9baa2 120000 (symlink)
--- a/cbmtof/cbmtof.vhd
+++ b/cbmtof/cbmtof.vhd
@@ -1 +1 @@
-currentRelease/cbmtof.vhd
\ No newline at end of file
+tdc_release/cbmtof.vhd
\ No newline at end of file

diff --git a/cbmtof/compile.pl b/cbmtof/compile.pl
new file mode 120000 (symlink)
index 0000000..4456748
--- /dev/null
+++ b/cbmtof/compile.pl
@@ -0,0 +1 @@
+../scripts/compile.pl
\ No newline at end of file

diff --git a/cbmtof/config.vhd b/cbmtof/config.vhd
index f48d2a86e807ef33d3c81d7b8abb316d9d2ddc48..76c5b969ddac2a43fa3b96c7207a3f9f03196626 100644 (file)
--- a/cbmtof/config.vhd
+++ b/cbmtof/config.vhd
@@ -12,8 +12,8 @@ package config is
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
   constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5;  -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
-  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons 
+  constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 2;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
@@ -35,7 +35,7 @@ package config is
 
 --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
   constant USE_125_MHZ              : integer := c_NO;  --not implemented yet!  
-  constant USE_RXCLOCK              : integer := c_YES;  --not implemented yet!
+  constant USE_RXCLOCK              : integer := c_NO;  --not implemented yet!
   constant USE_EXTERNALCLOCK        : integer := c_YES;
   constant USE_CLK_MANAGER_REF_TIME : integer := c_YES; --reference time through clk manager or direct
 

diff --git a/cbmtof/config_compile.pl b/cbmtof/config_compile.pl
new file mode 120000 (symlink)
index 0000000..67b86a0
--- /dev/null
+++ b/cbmtof/config_compile.pl
@@ -0,0 +1 @@
+config_compile_gsi.pl
\ No newline at end of file

diff --git a/cbmtof/config_compile_gsi.pl b/cbmtof/config_compile_gsi.pl
new file mode 100644 (file)
index 0000000..e683d9b
--- /dev/null
+++ b/cbmtof/config_compile_gsi.pl
@@ -0,0 +1,17 @@
+TOPNAME                      => "cbmtof",
+lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
+lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
+lattice_path                 => '/opt/lattice/diamond/3.4_x64/',
+synplify_path                => '/opt/synplicity/J-2014.09-SP2',
+#synplify_command             => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
+synplify_command             => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp",
+
+#Include only necessary lpf files
+include_TDC                  => 1,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+
+

diff --git a/cbmtof/currentRelease b/cbmtof/currentRelease
deleted file mode 120000 (symlink)
index bc38bfc..0000000
--- a/cbmtof/currentRelease
+++ /dev/null
@@ -1 +0,0 @@
-../tdc_releases/tdc_v2.1.2
\ No newline at end of file

diff --git a/cbmtof/tdc_release b/cbmtof/tdc_release
new file mode 120000 (symlink)
index 0000000..7733c1d
--- /dev/null
+++ b/cbmtof/tdc_release
@@ -0,0 +1 @@
+../../tdc/releases/tdc_v2.1.5
\ No newline at end of file

diff --git a/scripts/compile.pl b/scripts/compile.pl
index ef5f8c43179844bb198ab05ce17bfb813998ee52..f0b5452ef7983099eeff196d93b59f5ee7486f70 100755 (executable)
--- a/scripts/compile.pl
+++ b/scripts/compile.pl
@@ -128,6 +128,8 @@ if($include_TDC) {
   system("ln -s ../../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
 }
 
+system("cd workdir; ../../base/linkdesignfiles.sh; cd ..");
+
 #generate timestamp
 my $t=time;
 my $fh = new FileHandle(">version.vhd");