%\subsection{Memory Map}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-Register adddresses from 0xA000 to 0xA0ef is scm fpga (1)
-Register adddresses from 0xA0f0 to 0xA0ff is ecp2m fpga (2)
-Register adddresses from 0xA100 to 0xA100 + 10*Number of samples per beam structure (currently 50) is from scm fpga (1)
+Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1)
+Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2)
+Register addresses from 0xA100 to 0xA100 + 10*Number of samples per beam structure (currently 50) is from SCM FPGA (1)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CTS Control Registers}
\item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register xxx
\item[Bit 15] Enable beam inhibit to make system silent(only cal trigger are accepted) when there is no beam - look into beam inhibit signal settings register xxx
\item[Bit 16] Enable TOF/RPC to be a Start signal
- \item[Bit 23 -- 20] Set width for VETO signal used for anticoincidence logic - $value * 1.25\,ns$
+ \item[Bit 23 -- 20] Set width for VETO signal used for anti-coincidence logic - $value * 1.25\,ns$
\item[Bit 28] Select source for beam structure A - 0 Start, 1 RPC/TOF
\item[Bit 29] Select source for beam structure B - 0 Start, 1 RPC/TOF
\item[Bit 30] When set to '1' it generates RICH special APV trigger (double pulse on RICH connector) - edge sensitive 0 -> 1
- \item[Bit 31] Enable trigger line test, this works together with self trigger (set the requried frequency)
+ \item[Bit 31] Enable trigger line test, this works together with self trigger (set the required frequency)
\end{description}
\item [0xA0C1] LVL1/LVL2 trigger settings:
\begin{description}
- \item[Bit 16 -- 12] Delay (to the fastes trigger) of MDCB (MDC 3/4) trigger = value * 20 ns
+ \item[Bit 16 -- 12] Delay (to the feasts trigger) of MDCB (MDC 3/4) trigger = value * 20 ns
\item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns
\item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
\end{description}
\item 71 - 36 After delay
\item 72 - 107 After set width
\item 126 - 108 empty
- \item 127 - start signal used for anticoincidence logic (after OR)
- \item 128 - veto signal used for anticoincidence logic (after Width S.)
- \item 129 - antycoincidence signal
+ \item 127 - start signal used for anti-coincidence logic (after OR)
+ \item 128 - veto signal used for anti-coincidence logic (after Width S.)
+ \item 129 - inconsistency signal
\end{description}
\item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4))
\item[Bit 31 -- 28] Data version set into the data stream from the CTS (see CTS data structure chapter)
\item [0xA0C8] Sample period for 8 START channels - $value*100ns$ for individual start beam structure
\item [0xA0D0 -- 0xA0C9] Downscale registers - $2^{value}$
\item [0xA0D8 -- 0xA0D1] Delay registers - $value * 1,25\,ns$
- \item [0xA0D9] -- time offset for beam structrure A (after BEAM START signal)
- \item [0xA0DA] -- time offset for beam structrure B (after BEAM START signal)
- \item [0xA0DB] -- Sample period for beam structrure A - $value*100ns$
- \item [0xA0DC] -- Sample period for beam structrure B - $value*100ns$
+ \item [0xA0D9] -- time offset for beam structure A (after BEAM START signal)
+ \item [0xA0DA] -- time offset for beam structure B (after BEAM START signal)
+ \item [0xA0DB] -- Sample period for beam structure A - $value*100ns$
+ \item [0xA0DC] -- Sample period for beam structure B - $value*100NM$
\item [0xA0DD] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$
\item [0xA0E3] Self trigger
\begin{description}
\item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data
\begin{description}
\item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected
- \item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downsacling factor (counted per event) for transporting headers and trailers (bit 17 of the LVL1 trigger information).
+ \item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downscaling factor (counted per event) for transporting headers and trailers (bit 17 of the LVL1 trigger information).
\end{description}
\item [0xA0F1] LVL2 - events per EB
\begin{description}
\item[Bit 23 -- 0] Number of events per EB
\end{description}
- \item [0xA0F2] Mask for making busy based on LVL1 inforamtion sent back from the endpoints (when set to 1 and if lvl1 info is also 1 the busy will be created)
+ \item [0xA0F2] Mask for making busy based on LVL1 information sent back from the endpoints (when set to 1 and if LVL1 info is also 1 the busy will be created)
\end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item [0xA000] Trigger logic debug out
\begin{description}
\item[Bit 15 -- 0] LVL1 trigger number
- \item[Bit 16] trigger buffer fifo full
- \item[Bit 17] trigger buffer fifo empty
+ \item[Bit 16] trigger buffer FIFO full
+ \item[Bit 17] trigger buffer FIFO empty
\item[Bit 18] event rate bit 13
\item[Bit 19] event rate bit 15
- \item[Bit 20] lvl1 trigger buffer busy
- \item[Bit 21] lvl1 TrbNet busy
- \item[Bit 22] lvl1 local busy
- \item[Bit 31 -- 24] lvl1 trigger random code
+ \item[Bit 20] LVL1 trigger buffer busy
+ \item[Bit 21] LVL1 TrbNet busy
+ \item[Bit 22] LVL1 local busy
+ \item[Bit 31 -- 24] LVL1 trigger random code
\end{description}
- \item[0xA001: LVL1 information] Busy flags and current trigger number and type on LVL1 channel
+ \item[0xA001: LVL1 information] LVL1 trigger rate
\begin{description}
\item[Bit 19 -- 0] Accepted event rate
- \item[Bit 20] not used
- \item[Bit 21] not used
- \item[Bit 22] not used
- \item[Bit 23] 0
- \item[Bit 31 -- 24] LVL1 and LVL2 difference
+ \item[Bit 31 -- 20] not used
\end{description}
- \item[0xA002: Mixed information] LVL1 trigger rate, further busy flags for LVL1 and IPU channel
+ \item[0xA002: Mixed information] LVL1 state machine, beam inhibit and polarity
\begin{description}
- \item[Bit 15 -- 0] not used
- \item[Bit 19 -- 16] Trigger fifo data counter lower 4 bits
- \item[Bit 23 -- 20] LVL1 internal readout state machine :
+ \item[Bit 3 -- 0] LVL1 internal readout state machine :
\begin{description}
\item[0x0] Not allowed
\item[0x1] IDLE
\item[0x4] Data sending
\item[0x5] Data finished send
\end{description}
- \item[Bit 24] Beam inhibit in
+ \item[Bit 4] Beam inhibit signal created on base of START BEAM signal and register settings (0xA0DD)
+ \item[Bit 8 -- 5] PT 8 -- 5 polarity, if '1' then the polarity is not OK (expecting signals which most of the time are logically '0')
\end{description}
+ \item[0xA003: Polarity information]
+ \begin{description}
+ \item[Bit 31 -- 0] Polarity of input signals in order which corresponds to the Fig.\ref{cts_logic} (Start1, Start2, Start3,...Veto1,... ). If it is set to '1' then the polarity is not OK (expecting signals which most of the time are logically '0'). The polarity check is done already after inversion of signals in the FPGA (inverted polarities physically on the CTS trigger input)
+ \end{description}
+
\item[0xA004 : CTS readout to TrbNet]
\begin{description}
\item[Bit 15 -- 0] words in event
- \item[Bit 16] header fifo full
- \item[Bit 17] header fifo empty
- \item[Bit 18] data fifo full
- \item[Bit 19] data fifo empty
- \item[Bit 20] lvl2(second state machine runs directly after the first "lvl1") busy - in the state machine
- \item[Bit 21] lvl1 memory busy
- \item[Bit 22] lvl1 busy - in the state machine
+ \item[Bit 16] header FIFO full
+ \item[Bit 17] header FIFO empty
+ \item[Bit 18] data FIFO full
+ \item[Bit 19] data FIFO empty
+ \item[Bit 20] lvl2(second state machine runs directly after the first "LVL1") busy - in the state machine
+ \item[Bit 21] LVL1 memory busy
+ \item[Bit 22] LVL1 busy - in the state machine
\item[Bit 27 -- 24] first state machine debug
\begin{description}
\item[0x0] Not allowed
\begin{description}
\item[15 -- 0] LVL2 trigger number
\item[19 -- 16] LVL2 trigger buffer counter 3 -- 0
- \item[29--20] lvl1 triggers number -- lvl2 triggers numebr
- \item[30] LVL2 -> LVL1 back pressure busy (when LVL2 trigger fifo goes almost full)
- \item[31] Loccaly created LVL2 busy based on IPU TRBnet busy
+ \item[29--20] LVL1 triggers number -- lvl2 triggers number
+ \item[30] LVL2 -> LVL1 back pressure busy (when LVL2 trigger FIFO goes almost full)
+ \item[31] Locally created LVL2 busy based on IPU TRBnet busy
\end{description}
\item[0xA0F9] -- LVL1 information sent back from the endpoints
\item[0xA0FA]
\begin{description}
- \item[0] There is a lvl1 busy based on LVL1 informatio sent back from the endpoints
+ \item[0] There is a LVL1 busy based on LVL1 information sent back from the endpoints
\end{description}
\item[0xA131 - 0xA100] - beam structure A
\item[0xA163 - 0xA132] - beam structure B
- \item[0xA195 - 0xA164] - Start structure inout 1
- \item[0xA1C7 - 0xA96] - Start structure input 2
- \item[0xA164 - 0xA132] - Start structure input 3
- \item[0xA164 - 0xA132] - Start structure input 4
- \item[0xA164 - 0xA132] - Start structure input 5
- \item[0xA164 - 0xA132] - Start structure input 6
- \item[0xA164 - 0xA132] - Start structure input 7
+ \item[0xA195 - 0xA1C7] - Start structure input 1
+ \item[0xA1F9 - 0xA1C8] - Start structure input 2
+ \item[0xA22B - 0xA1FA] - Start structure input 3
+ \item[0xA25D - 0xA22C] - Start structure input 4
+ \item[0xA28F - 0xA25E] - Start structure input 5
+ \item[0xA2C1 - 0xA290] - Start structure input 6
+ \item[0xA2F3 - 0xA2C2] - Start structure input 7
\end{description}
When there is MDC calibration trigger CTS sends also scalers information.
\begin{description}
-\item[1 Standard hub word] When hub is used, currently without this (readout through etrax)
+\item[1 Standard hub word] When hub is used
\item[2 First header of the data] the same as for the timing detectors (Start,TOF ...)
\item[3 Second header]
\begin{description}
\item[bit 6] TOF/RPC multiplicity 5
\item[bit 7] TOF/RPC multiplicity 6
\item[bit 8] TOF/RPC multiplicity 2 no neigbour
- \item[bit 9] TOF/RPC multiplicity 3 no neighbour
+ \item[bit 9] TOF/RPC multiplicity 3 no neigbour
\item[bit 10] TOF/RPC multiplicity 2 opposite sectors
\item[bit 11] Physical trigger (PT) 1 (definition depends on the beam time)
\item[bit 12] PT 2
\item[bit 31 -- 19] All 0
\end{description}
\item[5 Latches] All 0
-\item[6 - XX] The rest of the data is just copy of all RW and R (for the scalers it is a copy of hits per second) registers (maximally up to the address 0xA0EF)
+\item[ - 6] The rest of the data is just copy of all RW and R (for the scalers it is a copy of hits per second) registers (maximally up to the address 0xA0EF)
\begin{description}
\item[6+RW registers(48)-1 -- 6] Register from 0xA0C0 address to 0xA0EC
\item[6+RW registers(48)+R registers(81)-1 -- 6+RW registers(48)] Register from 0xA000 address to 0xA051
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