-- File : TriggerHandler.vhd
-- Author : Cahit Ugur c.ugur@gsi.de
-- Created : 2013-03-13
--- Last update: 2014-05-06
+-- Last update: 2015-05-12
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library work;
--use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb3_components.all;
+use work.tdc_components.all;
entity TriggerHandler is
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.tdc_components.all;
+use work.config.all;
+use work.tdc_version.all;
+use work.version.all;
+
+
+entity trb3_periph_padiwa is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission.
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 6
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Manager 3
+ CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1
+ --CLK_PCLK_RIGHT is the only clock with external termination !?
+ CLK_EXTERNAL : in std_logic; --Clock Manager 9
+
+
+-- --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+-- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+
+ --Serdes
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
+ SERDES_TX : out std_logic_vector(3 downto 2);
+ SERDES_RX : in std_logic_vector(3 downto 2);
+
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+
+
+ --Connections
+ SPARE_LINE : inout std_logic_vector(3 downto 0);
+ INP : in std_logic_vector(63 downto 0);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --DAC
+ OUT_SDO : out std_logic_vector(4 downto 1);
+ IN_SDI : in std_logic_vector(4 downto 1);
+ OUT_SCK : out std_logic_vector(4 downto 1);
+ OUT_CS : out std_logic_vector(4 downto 1);
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of OUT_SCK : signal is true;
+ attribute syn_useioff of OUT_CS : signal is true;
+ attribute syn_useioff of OUT_SDO : signal is true;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+ attribute syn_useioff of SPARE_LINE : signal is true;
+ attribute syn_useioff of INP : signal is false;
+
+
+end entity;
+
+architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ signal clk_100_internal : std_logic;
+ signal clk_200_internal : std_logic;
+ signal rx_clock_100 : std_logic;
+ signal rx_clock_200 : std_logic;
+ signal clk_tdc : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i : std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic;
+ signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+ signal fee_data_i : std_logic_vector(31 downto 0);
+ signal fee_data_write_i : std_logic;
+ signal fee_data_finished_i : std_logic;
+ signal fee_almost_full_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ signal dac_read_en : std_logic;
+ signal dac_write_en : std_logic;
+ signal dac_data_in : std_logic_vector(31 downto 0);
+ signal dac_addr : std_logic_vector(4 downto 0);
+ signal dac_data_out : std_logic_vector(31 downto 0);
+ signal dac_ack : std_logic;
+ signal dac_busy : std_logic;
+
+ signal hitreg_read_en : std_logic;
+ signal hitreg_write_en : std_logic;
+ signal hitreg_data_in : std_logic_vector(31 downto 0);
+ signal hitreg_addr : std_logic_vector(6 downto 0);
+ signal hitreg_data_out : std_logic_vector(31 downto 0);
+ signal hitreg_data_ready : std_logic;
+ signal hitreg_invalid : std_logic;
+
+ signal srb_read_en : std_logic;
+ signal srb_write_en : std_logic;
+ signal srb_data_in : std_logic_vector(31 downto 0);
+ signal srb_addr : std_logic_vector(6 downto 0);
+ signal srb_data_out : std_logic_vector(31 downto 0);
+ signal srb_data_ready : std_logic;
+ signal srb_invalid : std_logic;
+
+ signal cdb_read_en : std_logic;
+ signal cdb_write_en : std_logic;
+ signal cdb_data_in : std_logic_vector(31 downto 0);
+ signal cdb_addr : std_logic_vector(6 downto 0);
+ signal cdb_data_out : std_logic_vector(31 downto 0);
+ signal cdb_data_ready : std_logic;
+ signal cdb_invalid : std_logic;
+
+ signal lhb_read_en : std_logic;
+ signal lhb_write_en : std_logic;
+ signal lhb_data_in : std_logic_vector(31 downto 0);
+ signal lhb_addr : std_logic_vector(6 downto 0);
+ signal lhb_data_out : std_logic_vector(31 downto 0);
+ signal lhb_data_ready : std_logic;
+ signal lhb_invalid : std_logic;
+
+ signal esb_read_en : std_logic;
+ signal esb_write_en : std_logic;
+ signal esb_data_in : std_logic_vector(31 downto 0);
+ signal esb_addr : std_logic_vector(6 downto 0);
+ signal esb_data_out : std_logic_vector(31 downto 0);
+ signal esb_data_ready : std_logic;
+ signal esb_invalid : std_logic;
+
+ signal efb_read_en : std_logic;
+ signal efb_write_en : std_logic;
+ signal efb_data_in : std_logic_vector(31 downto 0);
+ signal efb_addr : std_logic_vector(6 downto 0);
+ signal efb_data_out : std_logic_vector(31 downto 0);
+ signal efb_data_ready : std_logic;
+ signal efb_invalid : std_logic;
+
+ signal tdc_ctrl_read : std_logic;
+ signal last_tdc_ctrl_read : std_logic;
+ signal tdc_ctrl_write : std_logic;
+ signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
+ signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
+ signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
+ signal tdc_ctrl_reg : std_logic_vector(8*32-1 downto 0);
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+
+ signal padiwa_cs : std_logic_vector(3 downto 0);
+ signal padiwa_sck : std_logic;
+ signal padiwa_sdi : std_logic;
+ signal padiwa_sdo : std_logic;
+
+ signal trig_out : std_logic_vector(3 downto 0);
+ signal trig_din : std_logic_vector(31 downto 0);
+ signal trig_dout : std_logic_vector(31 downto 0);
+ signal trig_write : std_logic := '0';
+ signal trig_read : std_logic := '0';
+ signal trig_ack : std_logic := '0';
+ signal trig_nack : std_logic := '0';
+ signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal stat_out : std_logic_vector(3 downto 0);
+ signal stat_din : std_logic_vector(31 downto 0);
+ signal stat_dout : std_logic_vector(31 downto 0);
+ signal stat_write : std_logic := '0';
+ signal stat_read : std_logic := '0';
+ signal stat_ack : std_logic := '0';
+ signal stat_nack : std_logic := '0';
+ signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal sed_error : std_logic;
+ signal bussed_rx : CTRLBUS_RX;
+ signal bussed_tx : CTRLBUS_TX;
+
+ --TDC
+ signal hit_in_i : std_logic_vector(64 downto 1);
+ signal input_i : std_logic_vector(64 downto 1);
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_internal,
+ CLKOK => clk_200_internal,
+ LOCK => pll_lock
+ );
+
+ pll_calibration: entity work.pll_in125_out33
+ port map (
+ CLK => CLK_GPLL_LEFT,
+ CLKOP => osc_int,
+ LOCK => open);
+
+ gen_sync_clocks : if SYNC_MODE = c_YES generate
+ clk_100_i <= rx_clock_100;
+ clk_200_i <= rx_clock_200;
+ clk_tdc <= rx_clock_200;
+ end generate;
+
+ gen_local_clocks : if SYNC_MODE = c_NO generate
+ clk_100_i <= clk_100_internal;
+ clk_200_i <= clk_200_internal;
+ clk_tdc <= CLK_PCLK_LEFT;
+ end generate;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_RX(2),
+ SD_RXD_N_IN => SERDES_RX(3),
+ SD_TXD_P_OUT => SERDES_TX(2),
+ SD_TXD_N_OUT => SERDES_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => HARDWARE_INFO,
+ REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
+ REGIO_INIT_ADDRESS => INIT_ADDRESS,
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
+ FEE_DATA_IN => fee_data_i,
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i,
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 10,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"c100", 4 => x"b000",
+ 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", 9 => x"c200",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 7, 3 => 5, 4 => 9,
+ 5 => 3, 6 => 6, 7 => 7, 8 => 4, 9 => 7,
+ others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI Flash control)
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ --DAC
+ BUS_READ_ENABLE_OUT(1) => dac_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => dac_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => dac_data_in,
+ BUS_ADDR_OUT(1*16+4 downto 1*16) => dac_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => dac_data_out,
+ BUS_DATAREADY_IN(1) => dac_ack,
+ BUS_WRITE_ACK_IN(1) => dac_ack,
+ BUS_NO_MORE_DATA_IN(1) => dac_busy,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ --HitRegisters
+ BUS_READ_ENABLE_OUT(2) => hitreg_read_en,
+ BUS_WRITE_ENABLE_OUT(2) => hitreg_write_en,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => open,
+ BUS_ADDR_OUT(2*16+6 downto 2*16) => hitreg_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+7) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(2*32+31 downto 2*32) => hitreg_data_out,
+ BUS_DATAREADY_IN(2) => hitreg_data_ready,
+ BUS_WRITE_ACK_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => hitreg_invalid,
+ --Status Registers
+ BUS_READ_ENABLE_OUT(3) => srb_read_en,
+ BUS_WRITE_ENABLE_OUT(3) => srb_write_en,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => open,
+ BUS_ADDR_OUT(3*16+6 downto 3*16) => srb_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => srb_data_out,
+ BUS_DATAREADY_IN(3) => srb_data_ready,
+ BUS_WRITE_ACK_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => srb_invalid,
+ --SCI first Media Interface
+ BUS_READ_ENABLE_OUT(4) => sci1_read,
+ BUS_WRITE_ENABLE_OUT(4) => sci1_write,
+ BUS_DATA_OUT(4*32+7 downto 4*32) => sci1_data_in,
+ BUS_DATA_OUT(4*32+31 downto 4*32+8) => open,
+ BUS_ADDR_OUT(4*16+8 downto 4*16) => sci1_addr,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(4*32+7 downto 4*32) => sci1_data_out,
+ BUS_DATAREADY_IN(4) => sci1_ack,
+ BUS_WRITE_ACK_IN(4) => sci1_ack,
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
+ --TDC config registers
+ BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read,
+ BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write,
+ BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in,
+ BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr,
+ BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out,
+ BUS_DATAREADY_IN(5) => last_tdc_ctrl_read,
+ BUS_WRITE_ACK_IN(5) => tdc_ctrl_write,
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => '0',
+ --Trigger logic registers
+ BUS_READ_ENABLE_OUT(6) => trig_read,
+ BUS_WRITE_ENABLE_OUT(6) => trig_write,
+ BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din,
+ BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr,
+ BUS_TIMEOUT_OUT(6) => open,
+ BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout,
+ BUS_DATAREADY_IN(6) => trig_ack,
+ BUS_WRITE_ACK_IN(6) => trig_ack,
+ BUS_NO_MORE_DATA_IN(6) => '0',
+ BUS_UNKNOWN_ADDR_IN(6) => trig_nack,
+ --Input statistics
+ BUS_READ_ENABLE_OUT(7) => stat_read,
+ BUS_WRITE_ENABLE_OUT(7) => stat_write,
+ BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din,
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr,
+ BUS_TIMEOUT_OUT(7) => open,
+ BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout,
+ BUS_DATAREADY_IN(7) => stat_ack,
+ BUS_WRITE_ACK_IN(7) => stat_ack,
+ BUS_NO_MORE_DATA_IN(7) => '0',
+ BUS_UNKNOWN_ADDR_IN(7) => stat_nack,
+ --SEU Detection
+ BUS_READ_ENABLE_OUT(8) => bussed_rx.read,
+ BUS_WRITE_ENABLE_OUT(8) => bussed_rx.write,
+ BUS_DATA_OUT(8*32+31 downto 8*32) => bussed_rx.data,
+ BUS_ADDR_OUT(8*16+15 downto 8*16) => bussed_rx.addr,
+ BUS_TIMEOUT_OUT(8) => bussed_rx.timeout,
+ BUS_DATA_IN(8*32+31 downto 8*32) => bussed_tx.data,
+ BUS_DATAREADY_IN(8) => bussed_tx.ack,
+ BUS_WRITE_ACK_IN(8) => bussed_tx.ack,
+ BUS_NO_MORE_DATA_IN(8) => bussed_tx.nack,
+ BUS_UNKNOWN_ADDR_IN(8) => bussed_tx.unknown,
+ --Channel Debug Registers
+ BUS_READ_ENABLE_OUT(9) => cdb_read_en,
+ BUS_WRITE_ENABLE_OUT(9) => cdb_write_en,
+ BUS_DATA_OUT(9*32+31 downto 9*32) => open,
+ BUS_ADDR_OUT(9*16+6 downto 9*16) => cdb_addr,
+ BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open,
+ BUS_TIMEOUT_OUT(9) => open,
+ BUS_DATA_IN(9*32+31 downto 9*32) => cdb_data_out,
+ BUS_DATAREADY_IN(9) => cdb_data_ready,
+ BUS_WRITE_ACK_IN(9) => '0',
+ BUS_NO_MORE_DATA_IN(9) => '0',
+ BUS_UNKNOWN_ADDR_IN(9) => cdb_invalid,
+
+
+ STAT_DEBUG => open
+ );
+
+ PROC_TDC_CTRL_REG : process
+ variable pos : integer;
+ begin
+ wait until rising_edge(clk_100_i);
+ pos := to_integer(unsigned(tdc_ctrl_addr))*32;
+ tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
+ last_tdc_ctrl_read <= tdc_ctrl_read;
+ if tdc_ctrl_write = '1' then
+ tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+ THE_SPI_RELOAD : entity spi_flash_and_fpga_reload
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+---------------------------------------------------------------------------
+-- DAC
+---------------------------------------------------------------------------
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ THE_DAC_SPI : spi_ltc2600
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => dac_addr,
+ BUS_READ_IN => dac_read_en,
+ BUS_WRITE_IN => dac_write_en,
+ BUS_ACK_OUT => dac_ack,
+ BUS_BUSY_OUT => dac_busy,
+ BUS_DATA_IN => dac_data_in,
+ BUS_DATA_OUT => dac_data_out,
+ -- SPI connections
+ SPI_CS_OUT(3 downto 0) => padiwa_cs,
+ SPI_SDI_IN => padiwa_sdi,
+ SPI_SDO_OUT => padiwa_sdo,
+ SPI_SCK_OUT => padiwa_sck
+ );
+ OUT_CS <= padiwa_cs(3 downto 0);
+ OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
+ OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
+ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+ end generate;
+
+---------------------------------------------------------------------------
+-- Trigger logic
+---------------------------------------------------------------------------
+ gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ THE_TRIG_LOGIC : input_to_trigger_logic
+ generic map(
+ INPUTS => PHYSICAL_INPUTS,
+ OUTPUTS => 4
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => input_i(PHYSICAL_INPUTS downto 1),
+ OUTPUT => trig_out,
+
+ DATA_IN => trig_din,
+ DATA_OUT => trig_dout,
+ WRITE_IN => trig_write,
+ READ_IN => trig_read,
+ ACK_OUT => trig_ack,
+ NACK_OUT => trig_nack,
+ ADDR_IN => trig_addr
+ );
+ FPGA5_COMM(10 downto 7) <= trig_out;
+ end generate;
+
+---------------------------------------------------------------------------
+-- Input Statistics
+---------------------------------------------------------------------------
+ gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
+
+ THE_STAT_LOGIC : entity input_statistics
+ generic map(
+ INPUTS => PHYSICAL_INPUTS
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => input_i(PHYSICAL_INPUTS downto 1),
+
+ DATA_IN => stat_din,
+ DATA_OUT => stat_dout,
+ WRITE_IN => stat_write,
+ READ_IN => stat_read,
+ ACK_OUT => stat_ack,
+ NACK_OUT => stat_nack,
+ ADDR_IN => stat_addr
+ );
+ end generate;
+
+---------------------------------------------------------------------------
+-- SED Detection
+---------------------------------------------------------------------------
+ THE_SED : entity sedcheck
+ port map(
+ CLK => clk_100_i,
+ ERROR_OUT => sed_error,
+ BUS_RX => bussed_rx,
+ BUS_TX => bussed_tx
+ );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_ORANGE <= not reset_i when rising_edge(clk_100_i);
+ LED_YELLOW <= '1';
+ LED_GREEN <= not med_stat_op(9);
+ LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+-- TEST_LINE(15 downto 0) <= (others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_100_i);
+ time_counter <= time_counter + 1;
+ end process;
+
+
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : entity TDC
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
+ STATUS_REG_NR => 21, -- Number of status regs
+ CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ TDC_VERSION => TDC_VERSION,
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => clk_tdc, -- Clock used for the time measurement
+ CLK_READOUT => clk_100_i, -- Clock for the readout
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CALIBRATION => osc_int, -- Hits for calibrating the TDC
+ TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
+ TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
+ --
+ -- Trigger signals from handler
+ TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
+ VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
+ VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
+ INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
+ TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
+ SPIKE_DETECTED_IN => trg_spike_detected_i,
+ MULTI_TMG_TRG_IN => trg_multiple_trg_i,
+ SPURIOUS_TRG_IN => trg_spurious_trg_i,
+ --
+ TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
+ TRG_CODE_IN => trg_code_i, --
+ TRG_INFORMATION_IN => trg_information_i, --
+ TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
+ --
+ --Response to handler
+ TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
+ TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
+ DATA_OUT => fee_data_i, -- tdc data
+ DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
+ DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
+ --
+ --Hit Counter Bus
+ HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
+ HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
+ HCB_ADDR_IN => hitreg_addr, -- bus address
+ HCB_DATA_OUT => hitreg_data_out, -- bus data
+ HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
+ HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
+ --Status Registers Bus
+ SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
+ SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
+ SRB_ADDR_IN => srb_addr, -- bus address
+ SRB_DATA_OUT => srb_data_out, -- bus data
+ SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
+ SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
+ --Channel Debug Bus
+ CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe
+ CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe
+ CDB_ADDR_IN => cdb_addr, -- bus address
+ CDB_DATA_OUT => cdb_data_out, -- bus data
+ CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe
+ CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr
+ --Encoder Start Registers Bus
+ ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
+ ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
+ ESB_ADDR_IN => esb_addr, -- bus address
+ ESB_DATA_OUT => esb_data_out, -- bus data
+ ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
+ ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
+ --Fifo Write Registers Bus
+ EFB_READ_EN_IN => efb_read_en, -- bus read en strobe
+ EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe
+ EFB_ADDR_IN => efb_addr, -- bus address
+ EFB_DATA_OUT => efb_data_out, -- bus data
+ EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe
+ EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr
+ --Lost Hit Registers Bus
+ LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
+ LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
+ LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
+ LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
+ LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
+ LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
+ --
+ LOGIC_ANALYSER_OUT => TEST_LINE,
+ CONTROL_REG_IN => tdc_ctrl_reg);
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i <= INP;
+ input_i <= INP;
+ end generate;
+
+ -- For ToT Measurements
+ gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate
+ Gen_Hit_In_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i-1);
+ hit_in_i(i*2) <= not INP(i-1);
+ input_i(i) <= INP(i-1);
+ end generate Gen_Hit_In_Signals;
+ end generate;
+
+ gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate
+ Gen_Hit_Fast_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i*2-2);
+ hit_in_i(i*2) <= not INP(i*2-2);
+ input_i(i) <= INP(i*2-2);
+ end generate;
+ end generate;
+
+
+end architecture;
Q : out std_logic_vector(7 downto 0));
end component ROM4_Encoder;
+ component risingEdgeDetect is
+ port (
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+ end component risingEdgeDetect;
+
+ component fallingEdgeDetect is
+ port (
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+ end component fallingEdgeDetect;
+
+ component FIFO_36x128_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component FIFO_36x128_OutReg;
+
+ component FIFO_36x64_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ component FIFO_36x32_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component FIFO_36x32_OutReg;
+
+ component FIFO_36x16_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ component FIFO_DC_36x128_DynThr_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ AmFullThresh : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component FIFO_DC_36x128_DynThr_OutReg;
+
+ component FIFO_DC_36x128_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component FIFO_DC_36x128_OutReg;
+
+ component FIFO_DC_36x64_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component FIFO_DC_36x64_OutReg;
+
+ component FIFO_DC_36x32_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component FIFO_DC_36x16_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component ShiftRegisterSISO
+ generic (
+ DEPTH : integer range 1 to 32;
+ WIDTH : integer range 1 to 32);
+ port (
+ CLK : in std_logic;
+ D_IN : in std_logic_vector(WIDTH-1 downto 0);
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0));
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
end package tdc_components;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.tdc_components.all;
+use work.config.all;
+use work.tdc_version.all;
+use work.version.all;
+
+
+entity trb3_periph_padiwa is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission.
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 6
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Manager 3
+ CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1
+ --CLK_PCLK_RIGHT is the only clock with external termination !?
+ CLK_EXTERNAL : in std_logic; --Clock Manager 9
+
+
+-- --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+-- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+
+ --Serdes
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
+ SERDES_TX : out std_logic_vector(3 downto 2);
+ SERDES_RX : in std_logic_vector(3 downto 2);
+
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+
+
+ --Connections
+ SPARE_LINE : inout std_logic_vector(3 downto 0);
+ INP : in std_logic_vector(63 downto 0);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --DAC
+ OUT_SDO : out std_logic_vector(4 downto 1);
+ IN_SDI : in std_logic_vector(4 downto 1);
+ OUT_SCK : out std_logic_vector(4 downto 1);
+ OUT_CS : out std_logic_vector(4 downto 1);
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of OUT_SCK : signal is true;
+ attribute syn_useioff of OUT_CS : signal is true;
+ attribute syn_useioff of OUT_SDO : signal is true;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+ attribute syn_useioff of SPARE_LINE : signal is true;
+ attribute syn_useioff of INP : signal is false;
+
+
+end entity;
+
+architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ signal clk_100_internal : std_logic;
+ signal clk_200_internal : std_logic;
+ signal rx_clock_100 : std_logic;
+ signal rx_clock_200 : std_logic;
+ signal clk_tdc : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i : std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic;
+ signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+ signal fee_data_i : std_logic_vector(31 downto 0);
+ signal fee_data_write_i : std_logic;
+ signal fee_data_finished_i : std_logic;
+ signal fee_almost_full_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ signal dac_read_en : std_logic;
+ signal dac_write_en : std_logic;
+ signal dac_data_in : std_logic_vector(31 downto 0);
+ signal dac_addr : std_logic_vector(4 downto 0);
+ signal dac_data_out : std_logic_vector(31 downto 0);
+ signal dac_ack : std_logic;
+ signal dac_busy : std_logic;
+
+ signal hitreg_read_en : std_logic;
+ signal hitreg_write_en : std_logic;
+ signal hitreg_data_in : std_logic_vector(31 downto 0);
+ signal hitreg_addr : std_logic_vector(6 downto 0);
+ signal hitreg_data_out : std_logic_vector(31 downto 0);
+ signal hitreg_data_ready : std_logic;
+ signal hitreg_invalid : std_logic;
+
+ signal srb_read_en : std_logic;
+ signal srb_write_en : std_logic;
+ signal srb_data_in : std_logic_vector(31 downto 0);
+ signal srb_addr : std_logic_vector(6 downto 0);
+ signal srb_data_out : std_logic_vector(31 downto 0);
+ signal srb_data_ready : std_logic;
+ signal srb_invalid : std_logic;
+
+ signal cdb_read_en : std_logic;
+ signal cdb_write_en : std_logic;
+ signal cdb_data_in : std_logic_vector(31 downto 0);
+ signal cdb_addr : std_logic_vector(6 downto 0);
+ signal cdb_data_out : std_logic_vector(31 downto 0);
+ signal cdb_data_ready : std_logic;
+ signal cdb_invalid : std_logic;
+
+ signal lhb_read_en : std_logic;
+ signal lhb_write_en : std_logic;
+ signal lhb_data_in : std_logic_vector(31 downto 0);
+ signal lhb_addr : std_logic_vector(6 downto 0);
+ signal lhb_data_out : std_logic_vector(31 downto 0);
+ signal lhb_data_ready : std_logic;
+ signal lhb_invalid : std_logic;
+
+ signal esb_read_en : std_logic;
+ signal esb_write_en : std_logic;
+ signal esb_data_in : std_logic_vector(31 downto 0);
+ signal esb_addr : std_logic_vector(6 downto 0);
+ signal esb_data_out : std_logic_vector(31 downto 0);
+ signal esb_data_ready : std_logic;
+ signal esb_invalid : std_logic;
+
+ signal efb_read_en : std_logic;
+ signal efb_write_en : std_logic;
+ signal efb_data_in : std_logic_vector(31 downto 0);
+ signal efb_addr : std_logic_vector(6 downto 0);
+ signal efb_data_out : std_logic_vector(31 downto 0);
+ signal efb_data_ready : std_logic;
+ signal efb_invalid : std_logic;
+
+ signal tdc_ctrl_read : std_logic;
+ signal last_tdc_ctrl_read : std_logic;
+ signal tdc_ctrl_write : std_logic;
+ signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
+ signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
+ signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
+ signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0);
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+
+ signal padiwa_cs : std_logic_vector(3 downto 0);
+ signal padiwa_sck : std_logic;
+ signal padiwa_sdi : std_logic;
+ signal padiwa_sdo : std_logic;
+
+ signal trig_out : std_logic_vector(3 downto 0);
+ signal trig_din : std_logic_vector(31 downto 0);
+ signal trig_dout : std_logic_vector(31 downto 0);
+ signal trig_write : std_logic := '0';
+ signal trig_read : std_logic := '0';
+ signal trig_ack : std_logic := '0';
+ signal trig_nack : std_logic := '0';
+ signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal stat_out : std_logic_vector(3 downto 0);
+ signal stat_din : std_logic_vector(31 downto 0);
+ signal stat_dout : std_logic_vector(31 downto 0);
+ signal stat_write : std_logic := '0';
+ signal stat_read : std_logic := '0';
+ signal stat_ack : std_logic := '0';
+ signal stat_nack : std_logic := '0';
+ signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal sed_error : std_logic;
+ signal bussed_rx : CTRLBUS_RX;
+ signal bussed_tx : CTRLBUS_TX;
+
+ --TDC
+ signal hit_in_i : std_logic_vector(64 downto 1);
+ signal input_i : std_logic_vector(64 downto 1);
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_internal,
+ CLKOK => clk_200_internal,
+ LOCK => pll_lock
+ );
+
+ -- internal oscillator with frequency of 2.5MHz for tdc calibration
+ --OSCInst0 : OSCF
+ -- port map (
+ -- OSC => osc_int);
+ osc_int <= '0';
+
+ gen_sync_clocks : if SYNC_MODE = c_YES generate
+ clk_100_i <= rx_clock_100;
+ clk_200_i <= rx_clock_200;
+ clk_tdc <= rx_clock_200;
+ end generate;
+
+ gen_local_clocks : if SYNC_MODE = c_NO generate
+ clk_100_i <= clk_100_internal;
+ clk_200_i <= clk_200_internal;
+ clk_tdc <= CLK_PCLK_LEFT;
+ end generate;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_RX(2),
+ SD_RXD_N_IN => SERDES_RX(3),
+ SD_TXD_P_OUT => SERDES_TX(2),
+ SD_TXD_N_OUT => SERDES_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => HARDWARE_INFO,
+ REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
+ REGIO_INIT_ADDRESS => INIT_ADDRESS,
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 12,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**12-400,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
+ FEE_DATA_IN => fee_data_i,
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i,
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 10,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"c100", 4 => x"b000",
+ 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", 9 => x"c200",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 7, 3 => 5, 4 => 9,
+ 5 => 3, 6 => 6, 7 => 7, 8 => 4, 9 => 7,
+ others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI Flash control)
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ --DAC
+ BUS_READ_ENABLE_OUT(1) => dac_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => dac_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => dac_data_in,
+ BUS_ADDR_OUT(1*16+4 downto 1*16) => dac_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => dac_data_out,
+ BUS_DATAREADY_IN(1) => dac_ack,
+ BUS_WRITE_ACK_IN(1) => dac_ack,
+ BUS_NO_MORE_DATA_IN(1) => dac_busy,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ --HitRegisters
+ BUS_READ_ENABLE_OUT(2) => hitreg_read_en,
+ BUS_WRITE_ENABLE_OUT(2) => hitreg_write_en,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => open,
+ BUS_ADDR_OUT(2*16+6 downto 2*16) => hitreg_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+7) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(2*32+31 downto 2*32) => hitreg_data_out,
+ BUS_DATAREADY_IN(2) => hitreg_data_ready,
+ BUS_WRITE_ACK_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => hitreg_invalid,
+ --Status Registers
+ BUS_READ_ENABLE_OUT(3) => srb_read_en,
+ BUS_WRITE_ENABLE_OUT(3) => srb_write_en,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => open,
+ BUS_ADDR_OUT(3*16+6 downto 3*16) => srb_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => srb_data_out,
+ BUS_DATAREADY_IN(3) => srb_data_ready,
+ BUS_WRITE_ACK_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => srb_invalid,
+ --SCI first Media Interface
+ BUS_READ_ENABLE_OUT(4) => sci1_read,
+ BUS_WRITE_ENABLE_OUT(4) => sci1_write,
+ BUS_DATA_OUT(4*32+7 downto 4*32) => sci1_data_in,
+ BUS_DATA_OUT(4*32+31 downto 4*32+8) => open,
+ BUS_ADDR_OUT(4*16+8 downto 4*16) => sci1_addr,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(4*32+7 downto 4*32) => sci1_data_out,
+ BUS_DATAREADY_IN(4) => sci1_ack,
+ BUS_WRITE_ACK_IN(4) => sci1_ack,
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
+ --TDC config registers
+ BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read,
+ BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write,
+ BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in,
+ BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr,
+ BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out,
+ BUS_DATAREADY_IN(5) => last_tdc_ctrl_read,
+ BUS_WRITE_ACK_IN(5) => tdc_ctrl_write,
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => '0',
+ --Trigger logic registers
+ BUS_READ_ENABLE_OUT(6) => trig_read,
+ BUS_WRITE_ENABLE_OUT(6) => trig_write,
+ BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din,
+ BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr,
+ BUS_TIMEOUT_OUT(6) => open,
+ BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout,
+ BUS_DATAREADY_IN(6) => trig_ack,
+ BUS_WRITE_ACK_IN(6) => trig_ack,
+ BUS_NO_MORE_DATA_IN(6) => '0',
+ BUS_UNKNOWN_ADDR_IN(6) => trig_nack,
+ --Input statistics
+ BUS_READ_ENABLE_OUT(7) => stat_read,
+ BUS_WRITE_ENABLE_OUT(7) => stat_write,
+ BUS_DATA_OUT(7*32+31 downto 7*32) => stat_din,
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => stat_addr,
+ BUS_TIMEOUT_OUT(7) => open,
+ BUS_DATA_IN(7*32+31 downto 7*32) => stat_dout,
+ BUS_DATAREADY_IN(7) => stat_ack,
+ BUS_WRITE_ACK_IN(7) => stat_ack,
+ BUS_NO_MORE_DATA_IN(7) => '0',
+ BUS_UNKNOWN_ADDR_IN(7) => stat_nack,
+ --SEU Detection
+ BUS_READ_ENABLE_OUT(8) => bussed_rx.read,
+ BUS_WRITE_ENABLE_OUT(8) => bussed_rx.write,
+ BUS_DATA_OUT(8*32+31 downto 8*32) => bussed_rx.data,
+ BUS_ADDR_OUT(8*16+15 downto 8*16) => bussed_rx.addr,
+ BUS_TIMEOUT_OUT(8) => bussed_rx.timeout,
+ BUS_DATA_IN(8*32+31 downto 8*32) => bussed_tx.data,
+ BUS_DATAREADY_IN(8) => bussed_tx.ack,
+ BUS_WRITE_ACK_IN(8) => bussed_tx.ack,
+ BUS_NO_MORE_DATA_IN(8) => bussed_tx.nack,
+ BUS_UNKNOWN_ADDR_IN(8) => bussed_tx.unknown,
+ --Channel Debug Registers
+ BUS_READ_ENABLE_OUT(9) => cdb_read_en,
+ BUS_WRITE_ENABLE_OUT(9) => cdb_write_en,
+ BUS_DATA_OUT(9*32+31 downto 9*32) => open,
+ BUS_ADDR_OUT(9*16+6 downto 9*16) => cdb_addr,
+ BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open,
+ BUS_TIMEOUT_OUT(9) => open,
+ BUS_DATA_IN(9*32+31 downto 9*32) => cdb_data_out,
+ BUS_DATAREADY_IN(9) => cdb_data_ready,
+ BUS_WRITE_ACK_IN(9) => '0',
+ BUS_NO_MORE_DATA_IN(9) => '0',
+ BUS_UNKNOWN_ADDR_IN(9) => cdb_invalid,
+
+
+ STAT_DEBUG => open
+ );
+
+ PROC_TDC_CTRL_REG : process
+ variable pos : integer;
+ begin
+ wait until rising_edge(clk_100_i);
+ pos := to_integer(unsigned(tdc_ctrl_addr))*32;
+ tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
+ last_tdc_ctrl_read <= tdc_ctrl_read;
+ if tdc_ctrl_write = '1' then
+ tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+ THE_SPI_RELOAD : entity spi_flash_and_fpga_reload
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+---------------------------------------------------------------------------
+-- DAC
+---------------------------------------------------------------------------
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ THE_DAC_SPI : spi_ltc2600
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => dac_addr,
+ BUS_READ_IN => dac_read_en,
+ BUS_WRITE_IN => dac_write_en,
+ BUS_ACK_OUT => dac_ack,
+ BUS_BUSY_OUT => dac_busy,
+ BUS_DATA_IN => dac_data_in,
+ BUS_DATA_OUT => dac_data_out,
+ -- SPI connections
+ SPI_CS_OUT(3 downto 0) => padiwa_cs,
+ SPI_SDI_IN => padiwa_sdi,
+ SPI_SDO_OUT => padiwa_sdo,
+ SPI_SCK_OUT => padiwa_sck
+ );
+ OUT_CS <= padiwa_cs(3 downto 0);
+ OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
+ OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
+ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+ end generate;
+
+---------------------------------------------------------------------------
+-- Trigger logic
+---------------------------------------------------------------------------
+ gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ THE_TRIG_LOGIC : input_to_trigger_logic
+ generic map(
+ INPUTS => PHYSICAL_INPUTS,
+ OUTPUTS => 4
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => input_i(PHYSICAL_INPUTS downto 1),
+ OUTPUT => trig_out,
+
+ DATA_IN => trig_din,
+ DATA_OUT => trig_dout,
+ WRITE_IN => trig_write,
+ READ_IN => trig_read,
+ ACK_OUT => trig_ack,
+ NACK_OUT => trig_nack,
+ ADDR_IN => trig_addr
+ );
+ FPGA5_COMM(10 downto 7) <= trig_out;
+ end generate;
+
+---------------------------------------------------------------------------
+-- Input Statistics
+---------------------------------------------------------------------------
+ gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
+
+ THE_STAT_LOGIC : entity input_statistics
+ generic map(
+ INPUTS => PHYSICAL_INPUTS
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => input_i(PHYSICAL_INPUTS downto 1),
+
+ DATA_IN => stat_din,
+ DATA_OUT => stat_dout,
+ WRITE_IN => stat_write,
+ READ_IN => stat_read,
+ ACK_OUT => stat_ack,
+ NACK_OUT => stat_nack,
+ ADDR_IN => stat_addr
+ );
+ end generate;
+
+---------------------------------------------------------------------------
+-- SED Detection
+---------------------------------------------------------------------------
+ THE_SED : entity sedcheck
+ port map(
+ CLK => clk_100_i,
+ ERROR_OUT => sed_error,
+ BUS_RX => bussed_rx,
+ BUS_TX => bussed_tx
+ );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_ORANGE <= not reset_i when rising_edge(clk_100_i);
+ LED_YELLOW <= '1';
+ LED_GREEN <= not med_stat_op(9);
+ LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+-- TEST_LINE(15 downto 0) <= (others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_100_i);
+ time_counter <= time_counter + 1;
+ end process;
+
+
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : entity TDC
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
+ STATUS_REG_NR => 21, -- Number of status regs
+ CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ TDC_VERSION => TDC_VERSION, -- TDC version number
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => clk_tdc, -- Clock used for the time measurement
+ CLK_READOUT => clk_100_i, -- Clock for the readout
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC
+ TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
+ TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
+ --
+ -- Trigger signals from handler
+ TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
+ VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
+ VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
+ INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
+ TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
+ SPIKE_DETECTED_IN => trg_spike_detected_i,
+ MULTI_TMG_TRG_IN => trg_multiple_trg_i,
+ SPURIOUS_TRG_IN => trg_spurious_trg_i,
+ --
+ TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
+ TRG_CODE_IN => trg_code_i, --
+ TRG_INFORMATION_IN => trg_information_i, --
+ TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
+ --
+ --Response to handler
+ TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
+ TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
+ DATA_OUT => fee_data_i, -- tdc data
+ DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
+ DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
+ --
+ --Hit Counter Bus
+ HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
+ HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
+ HCB_ADDR_IN => hitreg_addr, -- bus address
+ HCB_DATA_OUT => hitreg_data_out, -- bus data
+ HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
+ HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
+ --Status Registers Bus
+ SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
+ SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
+ SRB_ADDR_IN => srb_addr, -- bus address
+ SRB_DATA_OUT => srb_data_out, -- bus data
+ SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
+ SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
+ --Channel Debug Bus
+ CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe
+ CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe
+ CDB_ADDR_IN => cdb_addr, -- bus address
+ CDB_DATA_OUT => cdb_data_out, -- bus data
+ CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe
+ CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr
+ --Encoder Start Registers Bus
+ ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
+ ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
+ ESB_ADDR_IN => esb_addr, -- bus address
+ ESB_DATA_OUT => esb_data_out, -- bus data
+ ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
+ ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
+ --Fifo Write Registers Bus
+ EFB_READ_EN_IN => efb_read_en, -- bus read en strobe
+ EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe
+ EFB_ADDR_IN => efb_addr, -- bus address
+ EFB_DATA_OUT => efb_data_out, -- bus data
+ EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe
+ EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr
+ --Lost Hit Registers Bus
+ LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
+ LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
+ LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
+ LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
+ LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
+ LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
+ --
+ LOGIC_ANALYSER_OUT => TEST_LINE,
+ CONTROL_REG_IN => tdc_ctrl_reg);
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i <= INP;
+ input_i <= INP;
+ end generate;
+
+ -- For ToT Measurements
+ gen_double : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 0 generate
+ Gen_Hit_In_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i-1);
+ hit_in_i(i*2) <= not INP(i-1);
+ input_i(i) <= INP(i-1);
+ end generate Gen_Hit_In_Signals;
+ end generate;
+
+ gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate
+ Gen_Hit_Fast_Signals : for i in 1 to 32 generate
+ hit_in_i(i*2-1) <= INP(i*2-2);
+ hit_in_i(i*2) <= not INP(i*2-2);
+ input_i(i) <= INP(i*2-2);
+ end generate;
+ end generate;
+
+
+end architecture;
+++ /dev/null
--------------------------------------------------------------------------------
--- Title : Channel 200 MHz Part
--- Project :
--------------------------------------------------------------------------------
--- File : Channel_200.vhd
--- Author : c.ugur@gsi.de
--- Created : 2012-08-28
--- Last update: 2015-05-13
--------------------------------------------------------------------------------
--- Description:
--------------------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.tdc_components.all;
-use work.config.all;
-
-entity Channel_200 is
-
- generic (
- CHANNEL_ID : integer range 0 to 64 := 1;
- DEBUG : integer range 0 to 1 := 1;
- SIMULATION : integer range 0 to 1 := 0;
- REFERENCE : integer range 0 to 1 := 0);
- port (
- CLK_200 : in std_logic; -- 200 MHz clk
- RESET_200 : in std_logic; -- reset sync with 200Mhz clk
- CLK_100 : in std_logic; -- 100 MHz clk
- RESET_100 : in std_logic; -- reset sync with 100Mhz clk
---
- HIT_IN : in std_logic; -- hit in
- HIT_EDGE_IN : in std_logic; -- hit edge in
- TRG_WIN_END_TDC_IN : in std_logic; -- trigger window end strobe
- TRG_WIN_END_RDO_IN : in std_logic; -- trigger window end strobe
- EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out
- FIFO_DATA_VALID_OUT : out std_logic; -- fifo data valid signal
- FIFO_ALMOST_FULL_OUT : out std_logic; -- fifo almost full signal ringbuffer overwrite detection
- RING_BUFFER_FULL_THRES_IN : in std_logic_vector(6 downto 0); -- ring buffer almost full threshold
---
- EPOCH_WRITE_EN_IN : in std_logic;
- ENCODER_START_OUT : out std_logic;
- ENCODER_FINISHED_OUT : out std_logic;
- FIFO_WRITE_OUT : out std_logic;
- CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0)
- );
-
-end Channel_200;
-
-architecture Channel_200 of Channel_200 is
-
- -- carry chain
- signal data_a : std_logic_vector(303 downto 0);
- signal data_b : std_logic_vector(303 downto 0);
- signal result : std_logic_vector(303 downto 0);
- signal thermocode : std_logic_vector(303 downto 0);
- signal ff_array_en : std_logic := '1';
-
- -- hit detection
- signal result_2_r : std_logic := '0';
- signal result_3_r : std_logic := '0';
- signal hit_detect : std_logic := '0';
- signal hit_detect_r : std_logic := '0';
- signal hit_detect_2r : std_logic := '0';
- signal edge_type : std_logic := '0';
- signal memory : std_logic_vector(1 downto 0) := (others => '0');
- signal wr_ptr : integer range 0 to 1 := 0;
- signal rd_ptr : integer range 0 to 1 := 0;
-
- -- time stamp
- signal time_stamp_array : std_logic_vector_array_11(3 downto 0);
- signal ts_wr_ptr : integer range 0 to 3 := 0;
- signal ts_rd_ptr : integer range 0 to 3 := 0;
- signal coarse_cntr_r : std_logic_vector(10 downto 0);
- signal coarse_cntr_overflow : std_logic_vector(0 downto 0);
- signal coarse_cntr_overflow_r : std_logic_vector(0 downto 0);
-
- -- encoder
- signal encoder_start : std_logic;
- signal encoder_finished : std_logic;
- signal encoder_data_out : std_logic_vector(9 downto 0);
- signal encoder_debug : std_logic_vector(31 downto 0);
-
- -- epoch counter
- signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0');
- signal epoch_cntr_updated : std_logic := '0';
- signal epoch_value : std_logic_vector(35 downto 0);
- signal epoch_value_r : std_logic_vector(35 downto 0);
-
- -- ring bugger
- signal ringBuffer_data_out : std_logic_vector(35 downto 0);
- signal ringBuffer_data_in : std_logic_vector(35 downto 0);
- signal ringBuffer_empty : std_logic;
- signal ringBuffer_full : std_logic;
- signal ringBuffer_almost_full_sync : std_logic;
- signal ringBuffer_almost_full : std_logic := '0';
- signal ringBuffer_almost_full_flag : std_logic := '0';
- signal ringBuffer_wr_en : std_logic;
- signal ringBuffer_rd_en : std_logic;
- signal ringBuffer_rd_data : std_logic;
- signal fifo_data : std_logic_vector(35 downto 0);
- signal fifo_data_valid : std_logic;
-
- -- fsm
- type FSM_WR is (IDLE, WRITE_DATA_WORD, WRITE_STOP_WORD_A, WRITE_STOP_WORD_B,
- WRITE_STOP_WORD_C, WRITE_STOP_WORD_D, WAIT_FOR_HIT, WAIT_FOR_VALIDITY,
- EXCEPTION);
- signal FSM_WR_CURRENT : FSM_WR;
- signal FSM_WR_NEXT : FSM_WR;
- signal write_epoch_fsm : std_logic;
- signal write_epoch : std_logic := '0';
- signal write_data_fsm : std_logic;
- signal write_data : std_logic := '0';
- signal write_stop_a_fsm : std_logic;
- signal write_stop_a : std_logic := '0';
- signal write_stop_b_fsm : std_logic;
- signal write_stop_b : std_logic := '0';
- signal write_data_flag_fsm : std_logic;
- signal write_data_flag : std_logic := '0';
- signal trg_win_end_tdc_flag : std_logic := '0';
- signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0);
- signal fsm_wr_debug : std_logic_vector(3 downto 0);
-
- type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C);
- signal FSM_RD_STATE : FSM_RD;
- signal trg_win_end_rdo_flag : std_logic := '0';
- signal fsm_rd_debug : std_logic_vector(3 downto 0);
-
- -----------------------------------------------------------------------------
- -- debug
- signal data_cnt_total : integer range 0 to 2147483647 := 0;
- signal data_cnt_event : integer range 0 to 255 := 0;
- signal epoch_cnt_total : integer range 0 to 65535 := 0;
- signal epoch_cnt_event : integer range 0 to 127 := 0;
- -----------------------------------------------------------------------------
-
- attribute syn_keep : boolean;
- attribute syn_keep of ff_array_en : signal is true;
-
-begin -- Channel_200
-
- SimAdderYes : if SIMULATION = c_YES generate
- --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition
- FC : Adder_304
- port map (
- CLK => CLK_200,
- RESET => RESET_200,
- DataA => data_a,
- DataB => data_b,
- ClkEn => ff_array_en,
- Result => result);
- data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000FFFFFFF"&x"7FFFFFF";
- data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN);
- end generate SimAdderYes;
- SimAdderNo : if SIMULATION = c_NO generate
- --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition
- FC : Adder_304
- port map (
- CLK => CLK_200,
- RESET => RESET_200,
- DataA => data_a,
- DataB => data_b,
- CLKEn => ff_array_en,
- Result => result);
- data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"7FFFFFF";
- data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN);
- end generate SimAdderNo;
-
- ff_array_en <= not(hit_detect or hit_detect_r); -- or hit_detect_2r);
-
- result_2_r <= result(2) when rising_edge(CLK_200);
- result_3_r <= result(3) when rising_edge(CLK_200);
--- hit_detect <= ((not result_2_r) and result(2)) or ((not result_3_r) and result(3)); -- detects the hit by
- hit_detect <= (not result_2_r) and result(2); -- detects the hit by
- -- comparing the
- -- previous state of the
- -- hit detection bit
-
- hit_detect_r <= hit_detect when rising_edge(CLK_200);
- hit_detect_2r <= hit_detect_r when rising_edge(CLK_200);
--- coarse_cntr_r <= COARSE_COUNTER_IN when rising_edge(CLK_200);
- encoder_start <= hit_detect; --hit_detect_r;
- ENCODER_START_OUT <= encoder_start;
-
- isReferenceEdge : if REFERENCE = c_YES or DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 2 generate
- edge_type <= '1';
- end generate isReferenceEdge;
-
- isChannelEdge : if REFERENCE = c_NO and (DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) generate
- EdgeTypeCapture : process (CLK_200) is
- begin -- process EdgeTypeCapture
- if rising_edge(CLK_200) then
- if hit_detect_2r = '1' then
- memory(wr_ptr) <= HIT_EDGE_IN;
- if wr_ptr = 1 then
- wr_ptr <= 0;
- else
- wr_ptr <= wr_ptr + 1;
- end if;
- end if;
- if encoder_finished = '1' then
- edge_type <= memory(rd_ptr);
- if rd_ptr = 1 then
- rd_ptr <= 0;
- else
- rd_ptr <= rd_ptr + 1;
- end if;
- end if;
- end if;
- end process EdgeTypeCapture;
- end generate isChannelEdge;
-
- TimeStampCapture : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if hit_detect_r = '1' then
- time_stamp_array(ts_wr_ptr) <= COARSE_COUNTER_IN;
- if ts_wr_ptr = 3 then
- ts_wr_ptr <= 0;
- else
- ts_wr_ptr <= ts_wr_ptr + 1;
- end if;
- end if;
- if write_data = '1' then
- if ts_rd_ptr = 3 then
- ts_rd_ptr <= 0;
- else
- ts_rd_ptr <= ts_rd_ptr + 1;
- end if;
- end if;
- end if;
- end process TimeStampCapture;
-
- CoarseCounterOverflow_1 : entity work.fallingEdgeDetect
- port map (
- CLK => CLK_200,
- SIGNAL_IN => COARSE_COUNTER_IN(10), -- coarse_cntr_r(10),
- PULSE_OUT => coarse_cntr_overflow(0));
-
- CoarseCounterOverflow_2 : entity work.ShiftRegisterSISO
- generic map (
- DEPTH => 6,
- WIDTH => 1)
- port map (
- CLK => CLK_200,
- D_IN => coarse_cntr_overflow,
- D_OUT => coarse_cntr_overflow_r);
-
- EpochCounterCapture : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if coarse_cntr_overflow_r(0) = '1' then
- epoch_cntr <= EPOCH_COUNTER_IN;
- epoch_cntr_updated <= '1';
- elsif write_epoch = '1' then
- epoch_cntr_updated <= '0';
- end if;
- end if;
- end process EpochCounterCapture;
-
- --purpose: Encoder
- Encoder : Encoder_304_Bit
- port map (
- RESET => RESET_200,
- CLK => CLK_200,
- START_IN => encoder_start,
- THERMOCODE_IN => thermocode, --result,
- FINISHED_OUT => encoder_finished,
- BINARY_CODE_OUT => encoder_data_out,
- ENCODER_DEBUG => encoder_debug);
- thermocode <= "11" & result(303 downto 2);
-
- RingBuffer_128_dyn : if RING_BUFFER_SIZE = 7 generate
- FIFO : FIFO_DC_36x128_DynThr_OutReg
- port map (
- Data => ringBuffer_data_in,
- WrClock => CLK_200,
- RdClock => CLK_100,
- WrEn => ringBuffer_wr_en,
- RdEn => ringBuffer_rd_en,
- Reset => RESET_100,
- RPReset => RESET_100,
- AmFullThresh => RING_BUFFER_FULL_THRES_IN,
- Q => ringBuffer_data_out,
- Empty => ringBuffer_empty,
- Full => ringBuffer_full,
- AlmostFull => ringBuffer_almost_full);
- end generate RingBuffer_128_dyn;
-
- RingBuffer_128 : if RING_BUFFER_SIZE = 3 generate
- FIFO : FIFO_DC_36x128_OutReg
- port map (
- Data => ringBuffer_data_in,
- WrClock => CLK_200,
- RdClock => CLK_100,
- WrEn => ringBuffer_wr_en,
- RdEn => ringBuffer_rd_en,
- Reset => RESET_100,
- RPReset => RESET_100,
- Q => ringBuffer_data_out,
- Empty => ringBuffer_empty,
- Full => ringBuffer_full,
- AlmostFull => ringBuffer_almost_full);
- end generate RingBuffer_128;
-
- RingBuffer_64 : if RING_BUFFER_SIZE = 1 generate
- FIFO : FIFO_DC_36x64_OutReg
- port map (
- Data => ringBuffer_data_in,
- WrClock => CLK_200,
- RdClock => CLK_100,
- WrEn => ringBuffer_wr_en,
- RdEn => ringBuffer_rd_en,
- Reset => RESET_100,
- RPReset => RESET_100,
- Q => ringBuffer_data_out,
- Empty => ringBuffer_empty,
- Full => ringBuffer_full,
- AlmostFull => ringBuffer_almost_full);
- end generate RingBuffer_64;
-
- RingBuffer_32 : if RING_BUFFER_SIZE = 0 generate
- FIFO : FIFO_DC_36x32_OutReg
- port map (
- Data => ringBuffer_data_in,
- WrClock => CLK_200,
- RdClock => CLK_100,
- WrEn => ringBuffer_wr_en,
- RdEn => ringBuffer_rd_en,
- Reset => RESET_100,
- RPReset => RESET_100,
- Q => ringBuffer_data_out,
- Empty => ringBuffer_empty,
- Full => ringBuffer_full,
- AlmostFull => ringBuffer_almost_full);
- end generate RingBuffer_32;
-
- ringBuffer_almost_full_sync <= ringBuffer_almost_full when rising_edge(CLK_100);
- ringBuffer_rd_en <= ringBuffer_rd_data or ringBuffer_almost_full_sync when rising_edge(CLK_100);
- FIFO_ALMOST_FULL_OUT <= ringBuffer_almost_full_flag;
-
- FifoAlmostEmptyFlag : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_100 = '1' then
- ringBuffer_almost_full_flag <= '0';
- elsif FSM_RD_STATE = READOUT_DATA_C then
- ringBuffer_almost_full_flag <= '0';
- elsif ringBuffer_almost_full_sync = '1' then
- ringBuffer_almost_full_flag <= '1';
- end if;
- end if;
- end process FifoAlmostEmptyFlag;
-
-
--------------------------------------------------------------------------------
--- Write Stage
--------------------------------------------------------------------------------
- -- Readout fsm
- FSM_CLK : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- FSM_WR_CURRENT <= IDLE;
- else
- FSM_WR_CURRENT <= FSM_WR_NEXT;
- write_epoch <= write_epoch_fsm;
- write_data <= write_data_fsm;
- write_stop_a <= write_stop_a_fsm;
- write_stop_b <= write_stop_b_fsm;
- write_data_flag <= write_data_flag_fsm;
- fsm_wr_debug <= fsm_wr_debug_fsm;
- end if;
- end if;
- end process FSM_CLK;
-
- FSM_PROC : process (FSM_WR_CURRENT, encoder_finished, epoch_cntr_updated, TRG_WIN_END_TDC_IN,
- trg_win_end_tdc_flag, write_data_flag)
- begin
-
- FSM_WR_NEXT <= IDLE;
- write_epoch_fsm <= '0';
- write_data_fsm <= '0';
- write_stop_a_fsm <= '0';
- write_stop_b_fsm <= '0';
- write_data_flag_fsm <= write_data_flag;
- fsm_wr_debug_fsm <= x"0";
-
- case (FSM_WR_CURRENT) is
- when IDLE =>
- if encoder_finished = '1' or write_data_flag = '1' then
- write_epoch_fsm <= '1';
- write_data_flag_fsm <= '0';
- FSM_WR_NEXT <= EXCEPTION;
- elsif trg_win_end_tdc_flag = '1' or TRG_WIN_END_TDC_IN = '1' then
- FSM_WR_NEXT <= WRITE_STOP_WORD_A;
- else
- write_epoch_fsm <= '0';
- FSM_WR_NEXT <= IDLE;
- end if;
- fsm_wr_debug_fsm <= x"1";
---
- when WRITE_DATA_WORD =>
- if epoch_cntr_updated = '1' then
- write_epoch_fsm <= '1';
- FSM_WR_NEXT <= EXCEPTION;
- else
- write_data_fsm <= '1';
- if trg_win_end_tdc_flag = '1' or TRG_WIN_END_TDC_IN = '1' then
- FSM_WR_NEXT <= WRITE_STOP_WORD_A;
- else
- FSM_WR_NEXT <= WAIT_FOR_HIT;
- end if;
- end if;
- fsm_wr_debug_fsm <= x"2";
---
- when EXCEPTION =>
- write_data_fsm <= '1';
- if trg_win_end_tdc_flag = '1' or TRG_WIN_END_TDC_IN = '1' then
- FSM_WR_NEXT <= WRITE_STOP_WORD_A;
- else
- FSM_WR_NEXT <= WAIT_FOR_HIT;
- end if;
- fsm_wr_debug_fsm <= x"3";
---
- when WAIT_FOR_HIT =>
- if epoch_cntr_updated = '1' and encoder_finished = '0' then
- FSM_WR_NEXT <= IDLE;
- elsif epoch_cntr_updated = '0' and encoder_finished = '1' then
- FSM_WR_NEXT <= WRITE_DATA_WORD;
- elsif epoch_cntr_updated = '1' and encoder_finished = '1' then
- FSM_WR_NEXT <= WRITE_DATA_WORD;
- elsif trg_win_end_tdc_flag = '1' or TRG_WIN_END_TDC_IN = '1' then
- FSM_WR_NEXT <= WRITE_STOP_WORD_A;
- else
- FSM_WR_NEXT <= WAIT_FOR_HIT;
- end if;
- fsm_wr_debug_fsm <= x"4";
---
- when WRITE_STOP_WORD_A =>
- write_stop_a_fsm <= '1';
- FSM_WR_NEXT <= WRITE_STOP_WORD_B;
- if encoder_finished = '1' then
- write_data_flag_fsm <= '1';
- end if;
- fsm_wr_debug_fsm <= x"5";
---
- when WRITE_STOP_WORD_B =>
- write_stop_a_fsm <= '1';
- FSM_WR_NEXT <= WRITE_STOP_WORD_C;
- if encoder_finished = '1' then
- write_data_flag_fsm <= '1';
- end if;
- fsm_wr_debug_fsm <= x"5";
---
- when WRITE_STOP_WORD_C =>
- write_stop_b_fsm <= '1';
- FSM_WR_NEXT <= WRITE_STOP_WORD_D;
- if encoder_finished = '1' then
- write_data_flag_fsm <= '1';
- end if;
- fsm_wr_debug_fsm <= x"5";
---
- when WRITE_STOP_WORD_D =>
- write_stop_b_fsm <= '1';
- FSM_WR_NEXT <= IDLE;
- if encoder_finished = '1' then
- write_data_flag_fsm <= '1';
- end if;
- fsm_wr_debug_fsm <= x"5";
---
- when others =>
- FSM_WR_NEXT <= IDLE;
- write_epoch_fsm <= '0';
- write_data_fsm <= '0';
- write_stop_a_fsm <= '0';
- write_stop_b_fsm <= '0';
- fsm_wr_debug_fsm <= x"0";
- end case;
- end process FSM_PROC;
-
- TriggerWindowFlag : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if RESET_200 = '1' then
- trg_win_end_tdc_flag <= '0';
- elsif TRG_WIN_END_TDC_IN = '1' then
- trg_win_end_tdc_flag <= '1';
- elsif FSM_WR_CURRENT = WRITE_STOP_WORD_D then
- trg_win_end_tdc_flag <= '0';
- end if;
- end if;
- end process TriggerWindowFlag;
-
- -- purpose: Generate Fifo Wr Signal
- FifoWriteSignal : process (CLK_200)
- begin
- if rising_edge(CLK_200) then
- if write_epoch = '1' and EPOCH_WRITE_EN_IN = '1' then
- ringBuffer_data_in(35 downto 32) <= x"1";
- ringBuffer_data_in(31 downto 29) <= "011";
- ringBuffer_data_in(28) <= '0';
- ringBuffer_data_in(27 downto 0) <= epoch_cntr;
- ringBuffer_wr_en <= '1';
- elsif write_data = '1' then
- ringBuffer_data_in(35 downto 32) <= x"1";
- ringBuffer_data_in(31) <= '1'; -- data marker
- ringBuffer_data_in(30 downto 29) <= "00"; -- reserved bits
- ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number
- ringBuffer_data_in(21 downto 12) <= encoder_data_out; -- fine time from the encoder
- ringBuffer_data_in(11) <= edge_type; -- rising '1' or falling '0' edge
- ringBuffer_data_in(10 downto 0) <= time_stamp_array(ts_rd_ptr); -- hit time stamp
- ringBuffer_wr_en <= '1';
- elsif write_stop_a = '1' then
- ringBuffer_data_in(35 downto 32) <= x"f";
- ringBuffer_data_in(31 downto 0) <= (others => '0');
- ringBuffer_wr_en <= '1';
- elsif write_stop_b = '1' then
- ringBuffer_data_in(35 downto 32) <= x"0";
- ringBuffer_data_in(31 downto 0) <= (others => '0');
- ringBuffer_wr_en <= '1';
- else
- ringBuffer_data_in(35 downto 32) <= x"e";
- ringBuffer_data_in(31 downto 0) <= (others => '0');
- ringBuffer_wr_en <= '0';
- end if;
- end if;
- end process FifoWriteSignal;
-
- FIFO_WRITE_OUT <= ringBuffer_wr_en;
- ENCODER_FINISHED_OUT <= encoder_finished;
-
--------------------------------------------------------------------------------
--- Read Stage
--------------------------------------------------------------------------------
- -- Determine the next state synchronously, based on the current state and the
- -- input
- FSM_DATA_STATE : process (CLK_100)
- begin
- if (rising_edge(CLK_100)) then
- if RESET_100 = '1' then
- FSM_RD_STATE <= IDLE;
- else
-
- case FSM_RD_STATE is
- when IDLE =>
- -- if the data readout is triggered by the end of the trigger window
- if TRG_WIN_END_RDO_IN = '1' then
- FSM_RD_STATE <= READOUT_DATA_A;
- -- if the data readout is triggered by full fifo
- elsif ringBuffer_almost_full_flag = '1' then
- FSM_RD_STATE <= FLUSH_D;
- else
- FSM_RD_STATE <= IDLE;
- end if;
- --
- when FLUSH_A =>
- FSM_RD_STATE <= FLUSH_D;
- --
- when FLUSH_B =>
- FSM_RD_STATE <= FLUSH_C;
- --
- when FLUSH_C =>
- FSM_RD_STATE <= FLUSH_D;
- --
- when FLUSH_D =>
- -- wait until a readout request and register the last epoch word
- if TRG_WIN_END_RDO_IN = '1' or trg_win_end_rdo_flag = '1' then
- FSM_RD_STATE <= READOUT_EPOCH;
- else
- FSM_RD_STATE <= FLUSH_D;
- end if;
- --
- when READOUT_EPOCH =>
- -- first epoch word should be readout
- FSM_RD_STATE <= READOUT_DATA_A;
- --
- when READOUT_DATA_A =>
- FSM_RD_STATE <= READOUT_DATA_B;
- --
- when READOUT_DATA_B =>
- FSM_RD_STATE <= READOUT_DATA_C;
- --
- when READOUT_DATA_C =>
- -- normal data readout until the end of the readout request
- if ringBuffer_data_out(35 downto 32) = x"f" then
- FSM_RD_STATE <= IDLE;
- else
- FSM_RD_STATE <= READOUT_DATA_C;
- end if;
- --
- when others =>
- FSM_RD_STATE <= IDLE;
- end case;
- end if;
- end if;
- end process FSM_DATA_STATE;
-
- -- Determine the output based only on the current state and the input (do not wait for a clock
- -- edge).
- FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRG_WIN_END_RDO_IN, ringBuffer_data_out, epoch_value)
- begin
- trg_win_end_rdo_flag <= trg_win_end_rdo_flag;
--- epoch_value <= epoch_value_r;
-
- case FSM_RD_STATE is
- when IDLE =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- fsm_rd_debug <= x"1";
- epoch_value <= x"100000000";
- when FLUSH_A =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- if TRG_WIN_END_RDO_IN = '1' then
- trg_win_end_rdo_flag <= '1';
- end if;
- fsm_rd_debug <= x"2";
- when FLUSH_B =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- if TRG_WIN_END_RDO_IN = '1' then
- trg_win_end_rdo_flag <= '1';
- end if;
- fsm_rd_debug <= x"3";
- when FLUSH_C =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- if TRG_WIN_END_RDO_IN = '1' then
- trg_win_end_rdo_flag <= '1';
- end if;
- fsm_rd_debug <= x"4";
- when FLUSH_D =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- if ringBuffer_data_out(31 downto 29) = "011" then
- epoch_value <= ringBuffer_data_out;
- end if;
- fsm_rd_debug <= x"5";
- when READOUT_EPOCH =>
- fifo_data <= epoch_value;
- fifo_data_valid <= '1';
- ringBuffer_rd_data <= '1';
- fsm_rd_debug <= x"6";
- when READOUT_DATA_A =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '1';
- trg_win_end_rdo_flag <= '0';
- fsm_rd_debug <= x"7";
- when READOUT_DATA_B =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '1';
- fsm_rd_debug <= x"8";
- when READOUT_DATA_C =>
- fifo_data <= ringBuffer_data_out;
- if ringBuffer_data_out(35 downto 32) = x"0" then
- fifo_data_valid <= '0';
- else
- fifo_data_valid <= '1';
- end if;
- ringBuffer_rd_data <= '1';
- fsm_rd_debug <= x"9";
- when others =>
- fifo_data <= (others => '0');
- fifo_data_valid <= '0';
- ringBuffer_rd_data <= '0';
- fsm_rd_debug <= x"0";
- end case;
- end process FSM_DATA_OUTPUT;
-
- epoch_value_r <= epoch_value when rising_edge(CLK_100);
- FIFO_DATA_OUT <= fifo_data;
- FIFO_DATA_VALID_OUT <= fifo_data_valid;
-
--------------------------------------------------------------------------------
--- DEBUG
--------------------------------------------------------------------------------
- --CHANNEL_200_DEBUG_OUT(7 downto 0) <= ringBuffer_data_in(35 downto 28);
- --CHANNEL_200_DEBUG_OUT(15 downto 8) <= fifo_data(35 downto 28);
- --CHANNEL_200_DEBUG_OUT(16) <= ringBuffer_wr_en;
- --CHANNEL_200_DEBUG_OUT(17) <= fifo_data_valid;
- --CHANNEL_200_DEBUG_OUT(18) <= ringBuffer_rd_en;
- --CHANNEL_200_DEBUG_OUT(23 downto 19) <= (others => '0');
- CHANNEL_200_DEBUG_OUT(23 downto 0) <= (others => '0');
- CHANNEL_200_DEBUG_OUT(27 downto 24) <= fsm_rd_debug;
- CHANNEL_200_DEBUG_OUT(31 downto 28) <= fsm_wr_debug;
-
- gen_SIMULATION : if SIMULATION = c_YES generate
- -- count data written
- data_cntr : process
- begin
- wait until rising_edge(CLK_100);
- if fifo_data_valid = '1' and fifo_data(31 downto 29) = "100" then
- data_cnt_event <= data_cnt_event + 1;
- elsif fifo_data_valid = '1' and fifo_data(31 downto 29) = "011" then
- epoch_cnt_event <= epoch_cnt_event + 1;
- elsif TRG_WIN_END_RDO_IN = '1' then
- data_cnt_event <= 0;
- epoch_cnt_event <= 0;
- end if;
- end process data_cntr;
-
- process(fifo_data_valid)
- begin -- process
- data_cnt_total <= data_cnt_total + data_cnt_event;
- epoch_cnt_total <= epoch_cnt_total + epoch_cnt_event;
- end process;
-
- -- check if data count per event is correct
- --CheckEpochCounter : process
- --begin
- -- wait until falling_edge(fifo_data_valid);
- -- wait for 1 ns;
- -- if data_cnt_event /= 30 then
- -- report "wrong number of hits in channel " & integer'image(CHANNEL_ID) severity error;
- -- end if;
- --end process CheckEpochCounter;
-
- end generate gen_SIMULATION;
-
-end Channel_200;
+++ /dev/null
-#################################################################
-# TDC Constraints
-#################################################################
-##############################################################################
-## DELAY LINE and HIT BUFFER PLACEMENTS ##
-##############################################################################
-##############################################################################
-UGROUP "Ref_Ch" BBOX 1 51
- BLKNAME THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "Ref_Ch" SITE "R32C2D" ;
-UGROUP "hitBuf_ref" BBOX 1 1
- BLKNAME THE_TDC/hit_mux_ref;
-LOCATE UGROUP "hitBuf_ref" SITE "R33C4D" ;
-UGROUP "Ref_ff_en" BBOX 1 1
- BLKNAME THE_TDC/ReferenceChannel/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "Ref_ff_en" SITE "R32C27D" ;
-#
-UGROUP "FC_1" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_1" SITE "R30C2D" ;
-UGROUP "hitBuf_1" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.1.hit_mux_ch;
-LOCATE UGROUP "hitBuf_1" SITE "R31C4D" ;
-UGROUP "ff_en_1" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_1" SITE "R30C27D" ;
-#
-UGROUP "FC_2" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_2" SITE "R48C2D" ;
-UGROUP "hitBuf_2" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.2.hit_mux_ch;
-LOCATE UGROUP "hitBuf_2" SITE "R49C4D" ;
-UGROUP "ff_en_2" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_2" SITE "R48C27D" ;
-#
-UGROUP "FC_3" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_3" SITE "R35C2D" ;
-UGROUP "hitBuf_3" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.3.hit_mux_ch;
-LOCATE UGROUP "hitBuf_3" SITE "R36C4D" ;
-UGROUP "ff_en_3" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_3" SITE "R35C27D" ;
-#
-UGROUP "FC_4" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_4" SITE "R37C2D" ;
-UGROUP "hitBuf_4" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.4.hit_mux_ch;
-LOCATE UGROUP "hitBuf_4" SITE "R38C4D" ;
-UGROUP "ff_en_4" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_4" SITE "R37C27D" ;
-#
-UGROUP "FC_5" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_5" SITE "R50C2D" ;
-UGROUP "hitBuf_5" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.5.hit_mux_ch;
-LOCATE UGROUP "hitBuf_5" SITE "R51C4D" ;
-UGROUP "ff_en_5" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_5" SITE "R50C27D" ;
-#
-UGROUP "FC_6" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_6" SITE "R71C2D" ;
-UGROUP "hitBuf_6" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.6.hit_mux_ch;
-LOCATE UGROUP "hitBuf_6" SITE "R72C4D" ;
-UGROUP "ff_en_6" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_6" SITE "R71C27D" ;
-#
-UGROUP "FC_7" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_7" SITE "R86C2D" ;
-UGROUP "hitBuf_7" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.7.hit_mux_ch;
-LOCATE UGROUP "hitBuf_7" SITE "R87C4D" ;
-UGROUP "ff_en_7" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_7" SITE "R86C27D" ;
-#
-UGROUP "FC_8" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_8" SITE "R84C2D" ;
-UGROUP "hitBuf_8" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.8.hit_mux_ch;
-LOCATE UGROUP "hitBuf_8" SITE "R85C4D" ;
-UGROUP "ff_en_8" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_8" SITE "R84C27D" ;
-#
-UGROUP "FC_9" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_9" SITE "R73C2D" ;
-UGROUP "hitBuf_9" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.9.hit_mux_ch;
-LOCATE UGROUP "hitBuf_9" SITE "R74C4D" ;
-UGROUP "ff_en_9" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_9" SITE "R73C27D" ;
-#
-UGROUP "FC_10" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_10" SITE "R102C2D" ;
-UGROUP "hitBuf_10" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.10.hit_mux_ch;
-LOCATE UGROUP "hitBuf_10" SITE "R103C4D" ;
-UGROUP "ff_en_10" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_10" SITE "R102C27D" ;
-#
-UGROUP "FC_11" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_11" SITE "R104C2D" ;
-UGROUP "hitBuf_11" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.11.hit_mux_ch;
-LOCATE UGROUP "hitBuf_11" SITE "R105C4D" ;
-UGROUP "ff_en_11" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_11" SITE "R104C27D" ;
-#
-UGROUP "FC_12" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_12" SITE "R91C2D" ;
-UGROUP "hitBuf_12" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.12.hit_mux_ch;
-LOCATE UGROUP "hitBuf_12" SITE "R92C4D" ;
-UGROUP "ff_en_12" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_12" SITE "R91C27D" ;
-#
-UGROUP "FC_13" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_13" SITE "R8C2D" ;
-UGROUP "hitBuf_13" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.13.hit_mux_ch;
-LOCATE UGROUP "hitBuf_13" SITE "R9C4D" ;
-UGROUP "ff_en_13" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_13" SITE "R8C27D" ;
-#
-UGROUP "FC_14" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_14" SITE "R10C2D" ;
-UGROUP "hitBuf_14" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.14.hit_mux_ch;
-LOCATE UGROUP "hitBuf_14" SITE "R11C4D" ;
-UGROUP "ff_en_14" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_14" SITE "R10C27D" ;
-#
-UGROUP "FC_15" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_15" SITE "R21C2D" ;
-UGROUP "hitBuf_15" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.15.hit_mux_ch;
-LOCATE UGROUP "hitBuf_15" SITE "R22C4D" ;
-UGROUP "ff_en_15" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_15" SITE "R21C27D" ;
-#
-UGROUP "FC_16" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_16" SITE "R23C2D" ;
-UGROUP "hitBuf_16" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.16.hit_mux_ch;
-LOCATE UGROUP "hitBuf_16" SITE "R24C4D" ;
-UGROUP "ff_en_16" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_16" SITE "R23C27D" ;
-#
-UGROUP "FC_17" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_17" SITE "R104C58D" ;
-UGROUP "hitBuf_17" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.17.hit_mux_ch;
-LOCATE UGROUP "hitBuf_17" SITE "R105C60D" ;
-UGROUP "ff_en_17" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_17" SITE "R104C83D" ;
-#
-UGROUP "FC_18" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_18" SITE "R89C58D" ;
-UGROUP "hitBuf_18" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.18.hit_mux_ch;
-LOCATE UGROUP "hitBuf_18" SITE "R90C60D" ;
-UGROUP "ff_en_18" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_18" SITE "R89C83D" ;
-#
-UGROUP "FC_19" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_19" SITE "R91C58D" ;
-UGROUP "hitBuf_19" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.19.hit_mux_ch;
-LOCATE UGROUP "hitBuf_19" SITE "R92C60D" ;
-UGROUP "ff_en_19" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_19" SITE "R91C83D" ;
-#
-UGROUP "FC_20" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_20" SITE "R102C58D" ;
-UGROUP "hitBuf_20" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.20.hit_mux_ch;
-LOCATE UGROUP "hitBuf_20" SITE "R103C60D" ;
-UGROUP "ff_en_20" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_20" SITE "R102C83D" ;
-#
-UGROUP "FC_21" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_21" SITE "R111C58D" ;
-UGROUP "hitBuf_21" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.21.hit_mux_ch;
-LOCATE UGROUP "hitBuf_21" SITE "R112C60D" ;
-UGROUP "ff_en_21" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_21" SITE "R111C83D" ;
-#
-UGROUP "FC_22" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_22" SITE "R113C58D" ;
-UGROUP "hitBuf_22" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.22.hit_mux_ch;
-LOCATE UGROUP "hitBuf_22" SITE "R114C60D" ;
-UGROUP "ff_en_22" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_22" SITE "R113C83D" ;
-#
-UGROUP "FC_23" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_23" SITE "R68C2D" ;
-UGROUP "hitBuf_23" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.23.hit_mux_ch;
-LOCATE UGROUP "hitBuf_23" SITE "R69C4D" ;
-UGROUP "ff_en_23" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_23" SITE "R68C27D" ;
-#
-UGROUP "FC_24" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_24" SITE "R55C2D" ;
-UGROUP "hitBuf_24" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.24.hit_mux_ch;
-LOCATE UGROUP "hitBuf_24" SITE "R56C4D" ;
-UGROUP "ff_en_24" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_24" SITE "R55C27D" ;
-#
-UGROUP "FC_25" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_25" SITE "R53C2D" ;
-UGROUP "hitBuf_25" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.25.hit_mux_ch;
-LOCATE UGROUP "hitBuf_25" SITE "R54C4D" ;
-UGROUP "ff_en_25" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_25" SITE "R53C27D" ;
-#
-UGROUP "FC_26" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_26" SITE "R66C2D" ;
-UGROUP "hitBuf_26" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.26.hit_mux_ch;
-LOCATE UGROUP "hitBuf_26" SITE "R67C4D" ;
-UGROUP "ff_en_26" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_26" SITE "R66C27D" ;
-#
-UGROUP "FC_27" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_27" SITE "R111C2D" ;
-UGROUP "hitBuf_27" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.27.hit_mux_ch;
-LOCATE UGROUP "hitBuf_27" SITE "R112C4D" ;
-UGROUP "ff_en_27" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_27" SITE "R111C27D" ;
-#
-UGROUP "FC_28" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_28" SITE "R113C2D" ;
-UGROUP "hitBuf_28" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.28.hit_mux_ch;
-LOCATE UGROUP "hitBuf_28" SITE "R114C4D" ;
-UGROUP "ff_en_28" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_28" SITE "R113C27D" ;
-#
-UGROUP "FC_29" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_29" SITE "R8C58D" ;
-UGROUP "hitBuf_29" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.29.hit_mux_ch;
-LOCATE UGROUP "hitBuf_29" SITE "R9C60D" ;
-UGROUP "ff_en_29" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_29" SITE "R8C83D" ;
-#
-UGROUP "FC_30" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_30" SITE "R10C58D" ;
-UGROUP "hitBuf_30" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.30.hit_mux_ch;
-LOCATE UGROUP "hitBuf_30" SITE "R11C60D" ;
-UGROUP "ff_en_30" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_30" SITE "R10C83D" ;
-#
-UGROUP "FC_31" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_31" SITE "R21C58D" ;
-UGROUP "hitBuf_31" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.31.hit_mux_ch;
-LOCATE UGROUP "hitBuf_31" SITE "R22C60D" ;
-UGROUP "ff_en_31" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_31" SITE "R21C83D" ;
-#
-UGROUP "FC_32" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_32" SITE "R23C58D" ;
-UGROUP "hitBuf_32" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.32.hit_mux_ch;
-LOCATE UGROUP "hitBuf_32" SITE "R24C60D" ;
-UGROUP "ff_en_32" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_32" SITE "R23C83D" ;
-#
-UGROUP "FC_33" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_33" SITE "R30C58D" ;
-UGROUP "hitBuf_33" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.33.hit_mux_ch;
-LOCATE UGROUP "hitBuf_33" SITE "R31C60D" ;
-UGROUP "ff_en_33" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_33" SITE "R30C83D" ;
-#
-UGROUP "FC_34" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_34" SITE "R32C58D" ;
-UGROUP "hitBuf_34" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.34.hit_mux_ch;
-LOCATE UGROUP "hitBuf_34" SITE "R33C60D" ;
-UGROUP "ff_en_34" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_34" SITE "R32C83D" ;
-#
-UGROUP "FC_35" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_35" SITE "R35C58D" ;
-UGROUP "hitBuf_35" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.35.hit_mux_ch;
-LOCATE UGROUP "hitBuf_35" SITE "R35C60D" ;
-UGROUP "ff_en_35" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_35" SITE "R35C83D" ;
-#
-UGROUP "FC_36" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_36" SITE "R37C58D" ;
-UGROUP "hitBuf_36" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.36.hit_mux_ch;
-LOCATE UGROUP "hitBuf_36" SITE "R38C60D" ;
-UGROUP "ff_en_36" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_36" SITE "R37C83D" ;
-#
-UGROUP "FC_37" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_37" SITE "R48C58D" ;
-UGROUP "hitBuf_37" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.37.hit_mux_ch;
-LOCATE UGROUP "hitBuf_37" SITE "R49C60D" ;
-UGROUP "ff_en_37" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_37" SITE "R48C83D" ;
-#
-UGROUP "FC_38" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_38" SITE "R50C58D" ;
-UGROUP "hitBuf_38" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.38.hit_mux_ch;
-LOCATE UGROUP "hitBuf_38" SITE "R51C60D" ;
-UGROUP "ff_en_38" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_38" SITE "R50C83D" ;
-#
-UGROUP "FC_39" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_39" SITE "R89C131D" ;
-UGROUP "hitBuf_39" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.39.hit_mux_ch;
-LOCATE UGROUP "hitBuf_39" SITE "R90C133D" ;
-UGROUP "ff_en_39" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_39" SITE "R89C156D" ;
-#
-UGROUP "FC_40" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_40" SITE "R91C131D" ;
-UGROUP "hitBuf_40" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.40.hit_mux_ch;
-LOCATE UGROUP "hitBuf_40" SITE "R92C133D" ;
-UGROUP "ff_en_40" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_40" SITE "R91C156D" ;
-#
-UGROUP "FC_41" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_41" SITE "R102C131D" ;
-UGROUP "hitBuf_41" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.41.hit_mux_ch;
-LOCATE UGROUP "hitBuf_41" SITE "R103C133D" ;
-UGROUP "ff_en_41" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_41" SITE "R102C156D" ;
-#
-UGROUP "FC_42" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_42" SITE "R104C131D" ;
-UGROUP "hitBuf_42" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.42.hit_mux_ch;
-LOCATE UGROUP "hitBuf_42" SITE "R105C133D" ;
-UGROUP "ff_en_42" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_42" SITE "R104C156D" ;
-#
-UGROUP "FC_43" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_43" SITE "R86C131D" ;
-UGROUP "hitBuf_43" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.43.hit_mux_ch;
-LOCATE UGROUP "hitBuf_43" SITE "R87C133D" ;
-UGROUP "ff_en_43" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_43" SITE "R86C156D" ;
-#
-UGROUP "FC_44" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_44" SITE "R84C131D" ;
-UGROUP "hitBuf_44" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.44.hit_mux_ch;
-LOCATE UGROUP "hitBuf_44" SITE "R85C133D" ;
-UGROUP "ff_en_44" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_44" SITE "R84C156D" ;
-#
-UGROUP "FC_45" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_45" SITE "R73C131D" ;
-UGROUP "hitBuf_45" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.45.hit_mux_ch;
-LOCATE UGROUP "hitBuf_45" SITE "R74C133D" ;
-UGROUP "ff_en_45" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_45" SITE "R73C156D" ;
-#
-UGROUP "FC_46" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_46" SITE "R71C131D" ;
-UGROUP "hitBuf_46" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.46.hit_mux_ch;
-LOCATE UGROUP "hitBuf_46" SITE "R72C133D" ;
-UGROUP "ff_en_46" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_46" SITE "R71C156D" ;
-#
-UGROUP "FC_47" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_47" SITE "R111C131D" ;
-UGROUP "hitBuf_47" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.47.hit_mux_ch;
-LOCATE UGROUP "hitBuf_47" SITE "R112C133D" ;
-UGROUP "ff_en_47" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_47" SITE "R111C156D" ;
-#
-UGROUP "FC_48" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_48" SITE "R113C131D" ;
-UGROUP "hitBuf_48" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.48.hit_mux_ch;
-LOCATE UGROUP "hitBuf_48" SITE "R114C133D" ;
-UGROUP "ff_en_48" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_48" SITE "R113C156D" ;
-#
-UGROUP "FC_49" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_49" SITE "R8C131D" ;
-UGROUP "hitBuf_49" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.49.hit_mux_ch;
-LOCATE UGROUP "hitBuf_49" SITE "R9C133D" ;
-UGROUP "ff_en_49" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_49" SITE "R8C156D" ;
-#
-UGROUP "FC_50" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_50" SITE "R10C131D" ;
-UGROUP "hitBuf_50" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.50.hit_mux_ch;
-LOCATE UGROUP "hitBuf_50" SITE "R11C133D" ;
-UGROUP "ff_en_50" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_50" SITE "R10C156D" ;
-#
-UGROUP "FC_51" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_51" SITE "R21C131D" ;
-UGROUP "hitBuf_51" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.51.hit_mux_ch;
-LOCATE UGROUP "hitBuf_51" SITE "R22C133D" ;
-UGROUP "ff_en_51" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_51" SITE "R21C156D" ;
-#
-UGROUP "FC_52" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_52" SITE "R23C131D" ;
-UGROUP "hitBuf_52" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.52.hit_mux_ch;
-LOCATE UGROUP "hitBuf_52" SITE "R24C133D" ;
-UGROUP "ff_en_52" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_52" SITE "R23C156D" ;
-#
-UGROUP "FC_53" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_53" SITE "R30C131D" ;
-UGROUP "hitBuf_53" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.53.hit_mux_ch;
-LOCATE UGROUP "hitBuf_53" SITE "R31C133D" ;
-UGROUP "ff_en_53" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_53" SITE "R30C156D" ;
-#
-UGROUP "FC_54" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_54" SITE "R32C131D" ;
-UGROUP "hitBuf_54" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.54.hit_mux_ch;
-LOCATE UGROUP "hitBuf_54" SITE "R33C133D" ;
-UGROUP "ff_en_54" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_54" SITE "R32C156D" ;
-#
-UGROUP "FC_55" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_55" SITE "R35C131D" ;
-UGROUP "hitBuf_55" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.55.hit_mux_ch;
-LOCATE UGROUP "hitBuf_55" SITE "R36C133D" ;
-UGROUP "ff_en_55" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_55" SITE "R35C156D" ;
-#
-UGROUP "FC_56" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_56" SITE "R37C131D" ;
-UGROUP "hitBuf_56" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.56.hit_mux_ch;
-LOCATE UGROUP "hitBuf_56" SITE "R38C133D" ;
-UGROUP "ff_en_56" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_56" SITE "R37C156D" ;
-#
-UGROUP "FC_57" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_57" SITE "R48C131D" ;
-UGROUP "hitBuf_57" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.57.hit_mux_ch;
-LOCATE UGROUP "hitBuf_57" SITE "R49C133D" ;
-UGROUP "ff_en_57" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_57" SITE "R48C156D" ;
-#
-UGROUP "FC_58" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_58" SITE "R50C131D" ;
-UGROUP "hitBuf_58" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.58.hit_mux_ch;
-LOCATE UGROUP "hitBuf_58" SITE "R51C133D" ;
-UGROUP "ff_en_58" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_58" SITE "R50C156D" ;
-#
-UGROUP "FC_59" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_59" SITE "R53C131D" ;
-UGROUP "hitBuf_59" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.59.hit_mux_ch;
-LOCATE UGROUP "hitBuf_59" SITE "R54C133D" ;
-UGROUP "ff_en_59" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_59" SITE "R53C156D" ;
-#
-UGROUP "FC_60" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_60" SITE "R55C131D" ;
-UGROUP "hitBuf_60" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.60.hit_mux_ch;
-LOCATE UGROUP "hitBuf_60" SITE "R56C133D" ;
-UGROUP "ff_en_60" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_60" SITE "R55C156D" ;
-#
-UGROUP "FC_61" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_61" SITE "R66C131D" ;
-UGROUP "hitBuf_61" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.61.hit_mux_ch;
-LOCATE UGROUP "hitBuf_61" SITE "R67C133D" ;
-UGROUP "ff_en_61" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_61" SITE "R66C156D" ;
-#
-UGROUP "FC_62" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_62" SITE "R68C131D" ;
-UGROUP "hitBuf_62" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.62.hit_mux_ch;
-LOCATE UGROUP "hitBuf_62" SITE "R69C133D" ;
-UGROUP "ff_en_62" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_62" SITE "R68C156D" ;
-#
-UGROUP "FC_63" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_63" SITE "R86C58D" ;
-UGROUP "hitBuf_63" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.63.hit_mux_ch;
-LOCATE UGROUP "hitBuf_63" SITE "R87C60D" ;
-UGROUP "ff_en_63" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_63" SITE "R86C83D" ;
-#
-UGROUP "FC_64" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200/SimAdderNo.FC;
-LOCATE UGROUP "FC_64" SITE "R84C58D" ;
-UGROUP "hitBuf_64" BBOX 1 1
- BLKNAME THE_TDC/GEN_hit_mux.64.hit_mux_ch;
-LOCATE UGROUP "hitBuf_64" SITE "R85C60D" ;
-UGROUP "ff_en_64" BBOX 1 1
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en_1_i;
-LOCATE UGROUP "ff_en_64" SITE "R84C83D" ;
-#
-
-
-##############################################################################
-## CHANNEL PLACEMENTS ##
-##############################################################################
-UGROUP "EF_LT2" BBOX 10 54
- BLKNAME THE_TDC/ReferenceChannel/Channel200
- BLKNAME THE_TDC/ReferenceChannel/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LT2" SITE "R24C2D" ;
-UGROUP "EF_LC1" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.2.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.3.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.4.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.5.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LC1" SITE "R35C2D" ;
-UGROUP "EF_LC3" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.6.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.7.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.8.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.9.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LC3" SITE "R71C2D" ;
-UGROUP "EF_LB1" BBOX 16 54
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.10.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.11.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.12.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LB1" SITE "R89C2D" ;
-UGROUP "EF_LT1" BBOX 16 54
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.13.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.14.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.15.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.16.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LT1" SITE "R8C2D" ;
-UGROUP "EF_CB1" BBOX 16 54
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.17.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.18.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.19.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.20.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_CB1" SITE "R89C56D" ;
-UGROUP "EF_CB2" BBOX 10 54
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.21.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.22.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_CB2" SITE "R105C56D" ;
-UGROUP "EF_LC2" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.23.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.24.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.25.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.26.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LC2" SITE "R53C2D" ;
-UGROUP "EF_LB2" BBOX 10 54
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.27.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.28.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_LB2" SITE "R105C2D" ;
-UGROUP "EF_CT1" BBOX 16 54
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.30.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.31.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_CT1" SITE "R8C56D" ;
-UGROUP "EF_CT2" BBOX 10 54
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.33.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.34.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_CT2" SITE "R24C56D" ;
-UGROUP "EF_CC1" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.35.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.36.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.37.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.38.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_CC1" SITE "R35C56D" ;
-UGROUP "EF_RB1" BBOX 16 54
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.39.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.40.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.41.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.42.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RB1" SITE "R89C128D" ;
-UGROUP "EF_RC3" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.43.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.44.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.45.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.46.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RC3" SITE "R71C128D" ;
-UGROUP "EF_RB2" BBOX 10 54
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.47.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.48.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RB2" SITE "R105C128D" ;
-UGROUP "EF_RT1" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.49.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.50.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.51.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.52.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RT1" SITE "R8C128D" ;
-UGROUP "EF_RT2" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.53.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.54.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RT2" SITE "R24C128D" ;
-UGROUP "EF_RC1" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.55.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.56.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.57.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.58.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RC1" SITE "R35C128D" ;
-UGROUP "EF_RC2" BBOX 17 54
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.59.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.60.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.61.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.62.Channels/Buffer_128.The_Buffer
- ;
-LOCATE UGROUP "EF_RC2" SITE "R53C128D" ;
-UGROUP "EF_CC3" BBOX 10 54
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.63.Channels/Buffer_128.The_Buffer
- BLKNAME THE_TDC/GEN_Channels.64.Channels/Buffer_128.The_Buffer;
-LOCATE UGROUP "EF_CC3" SITE "R78C56D" ;
-
-# #############################################################################
-# ## Stretcher
-# #############################################################################
-# UGROUP "Stretcher_A" BBOX 6 8
-# BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_A_1
-# ;
-# LOCATE UGROUP "Stretcher_A" SITE "R2C174D";
-
-# UGROUP "Stretcher_B" BBOX 6 8
-# BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_B_1
-# ;
-# LOCATE UGROUP "Stretcher_B" SITE "R2C2D";
-
-#############################################################################
-## Coarse counter register placement
-#############################################################################
-
-#############################################################################
-## Other Logic Placements
-#############################################################################
-
-
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ;
-
-PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.2.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.3.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.4.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.5.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.6.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.7.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.8.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.9.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.10.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.11.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.12.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.13.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.14.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.15.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.16.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.17.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.18.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.19.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.20.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.21.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.22.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.23.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.24.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.25.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.26.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.27.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.28.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.31.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.32.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.33.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.34.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.35.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.36.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.37.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.38.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.39.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.40.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.41.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.42.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.43.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.44.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.45.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.46.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.47.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.48.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.58.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.59.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.60.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en";
-PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en";
jspc29 / tdc.git / commitdiff