--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n lattice_ecp2m_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf 1020 -e
+
+-- Tue Jun 29 10:53:52 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_ecp2m_fifo_18x1k is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_ecp2m_fifo_18x1k;
+
+architecture Structure of lattice_ecp2m_fifo_18x1k is
+
+ -- internal signal declarations
+ signal partial_empty: std_logic;
+ signal scuba_vhi: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vlo: std_logic;
+ signal low_1: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b011111111100001";
+ attribute FULLPOINTER of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b011111111110001";
+ attribute AFPOINTER1 of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b011111110100001";
+ attribute AFPOINTER of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b011111110110001";
+ attribute AEPOINTER1 of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b000000000001111";
+ attribute AEPOINTER of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b111111111111111";
+ attribute RESETMODE of lattice_ecp2m_fifo_18x1k_0_0 : label is "ASYNC";
+ attribute REGMODE of lattice_ecp2m_fifo_18x1k_0_0 : label is "NOREG";
+ attribute CSDECODE_R of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b11";
+ attribute CSDECODE_W of lattice_ecp2m_fifo_18x1k_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of lattice_ecp2m_fifo_18x1k_0_0 : label is "18";
+ attribute DATA_WIDTH_W of lattice_ecp2m_fifo_18x1k_0_0 : label is "18";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ lattice_ecp2m_fifo_18x1k_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001",
+ AFPOINTER1=> "011111110100001", AFPOINTER=> "011111110110001",
+ AEPOINTER1=> "000000000001111", AEPOINTER=> "111111111111111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), DI18=>low_1,
+ DI19=>low_1, DI20=>low_1, DI21=>low_1, DI22=>low_1,
+ DI23=>low_1, DI24=>low_1, DI25=>low_1, DI26=>low_1,
+ DI27=>low_1, DI28=>low_1, DI29=>low_1, DI30=>low_1,
+ DI31=>low_1, DI32=>low_1, DI33=>low_1, DI34=>low_1,
+ DI35=>low_1, FULLI=>Full_int, CSW0=>scuba_vhi,
+ CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi,
+ CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>Clock,
+ CLKR=>Clock, RST=>Reset, RPRST=>scuba_vlo, DO0=>Q(0),
+ DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
+ DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>Q(9), DO10=>Q(10),
+ DO11=>Q(11), DO12=>Q(12), DO13=>Q(13), DO14=>Q(14),
+ DO15=>Q(15), DO16=>Q(16), DO17=>Q(17), DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open, EF=>Empty_int, AEF=>partial_empty,
+ AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_ecp2m_fifo_18x1k is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
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