Found some errors during simulation in trigger handler and mupix interface

diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd
index 78b6589d875f645d8eb9a505f2bb65f6553e904b..e9967945d1c8d57b5e811c1fa971ae23921164ac 100644 (file)
--- a/mupix/sources/MuPix3_interface.vhd
+++ b/mupix/sources/MuPix3_interface.vhd
@@ -94,6 +94,8 @@ architecture RTL of mupix_interface is
   signal rocontrolbits        : std_logic_vector(31 downto 0) := (others => '0');
   signal timestampcontrolbits : std_logic_vector(31 downto 0) := (others => '0');
   signal generatehitswait     : std_logic_vector(31 downto 0) := (others => '0');
+
+  signal priout_reg : std_logic := '0';
   
 begin
 
@@ -257,7 +259,7 @@ begin
           endofevent   <= '0';
         when pause =>
           pausecounter <= pausecounter +1;
-          if(pausecounter = pauseregister) then
+          if(std_logic_vector(pausecounter) = pauseregister) then
             state        <= waiting;
             pausecounter <= (others => '0');
           end if;
@@ -377,13 +379,13 @@ begin
           memwren      <= '0';
           state        <= readcol;
           endofevent   <= '0';
-          if (delcounter = delaycounter(27 downto 24)) then
+          if (std_logic_vector(delcounter) = delaycounters(27 downto 24)) then
             priout_reg <= priout;
           end if;
-          if(delcounter = delaycounter(31 downto 28)) then
+          if(std_logic_vector(delcounter) = delaycounters(31 downto 28)) then
             memdata    <= "111100001111" & hit_col & hit_row & hit_time;  --0xF0F
             memwren    <= '1';
-            hitcounter <= hitcounter + '1';
+            hitcounter <= hitcounter + 1;
             state      <= readcol;
           elsif(delcounter = "0000" and hitcounter = "11111111111") then
             -- 2048 hits - this makes no sense
@@ -392,7 +394,7 @@ begin
             memdata    <= "10111110111011111011111011101111";  --0xBEEFBEEF
             endofevent <= '1';
             state      <= pause;
-          elsif(delcounter = "0000" and priout = '1') then
+          elsif(delcounter = "0000" and (priout = '1' or (delaycounters(27 downto 24) /= "0000" and priout_reg = '1'))) then
             state      <= readcol;
             rdcol      <= '1';
             delcounter <= unsigned(delaycounters(15 downto 12));

diff --git a/mupix/sources/TriggerHanlder.vhd b/mupix/sources/TriggerHandler.vhd
similarity index 96%
rename from mupix/sources/TriggerHanlder.vhd
rename to mupix/sources/TriggerHandler.vhd
index e6d16a72f3913c443d82b05ef00acb40723a6e11..710150dcfc1d826e4eec2c06e1b05d4f6825a1da 100644 (file)
--- a/mupix/sources/TriggerHanlder.vhd
+++ b/mupix/sources/TriggerHandler.vhd
@@ -67,6 +67,7 @@ architecture behavioral of TriggerHandler is
 --trigger 
   signal valid_trigger_int       : std_logic                     := '0';
   signal timing_trigger_int      : std_logic                     := '0';
+  signal timing_trigger_edge     : std_logic_vector(1 downto 0)  := "00";
   signal status_trigger_int      : std_logic                     := '0';
   signal calibration_trigger_int : std_logic                     := '0';
   signal fast_clear_int          : std_logic                     := '0';
@@ -90,7 +91,7 @@ architecture behavioral of TriggerHandler is
   signal trigger_rate_time_counter : unsigned(31 downto 0) := (others => '0');
   signal invalid_trigger_counter : unsigned(31 downto 0);
   signal valid_trigger_counter : unsigned(31 downto 0) := (others => '0');
-  signal invalid_trigger_counter_t : unsigned(31 downto 0);
+  signal invalid_trigger_counter_t : unsigned(31 downto 0)  := (others => '0');
   signal valid_trigger_counter_t : unsigned(31 downto 0) := (others => '0');
   signal trigger_handler_state : std_logic_vector(7 downto 0);
   
@@ -120,12 +121,13 @@ architecture behavioral of TriggerHandler is
   
 begin
   
-  Mupix_Readout_End_Detect: process (CLK_IN) is
+  Signal_Edge_Detect: process (CLK_IN) is
   begin  -- process Mupix_Readout_End_Detect
     if rising_edge(CLK_IN) then
       mupix_readout_end_int <= mupix_readout_end_int(0) & TRIGGER_BUSY_MUPIX_DATA_IN;
+      timing_trigger_edge <= timing_trigger_edge(0) & TIMING_TRIGGER_IN;
     end if;
-  end process Mupix_Readout_End_Detect;
+  end process Signal_Edge_Detect;
 
   ------------------------------------------------------------
   --Handling of LVL1 triggers
@@ -136,6 +138,8 @@ begin
     valid_trigger_int       <= '0';
     timing_trigger_int      <= '0';
     status_trigger_int      <= '0';
+    flush_buffer_int        <= '0';
+    fee_data_write_int      <= '0';
     fee_data_finished_int   <= '0';
     fee_trg_release_int     <= '0';
     fee_trg_statusbit_int   <= (others => '0');
@@ -255,10 +259,11 @@ begin
         trigger_rate_time_counter <= (others => '0');
       end if;
       if trigger_rate_time_counter < x"5f5e100" then--1s at 10ns clock period
+      --if trigger_rate_time_counter < x"000007e" then
         trigger_rate_time_counter <= trigger_rate_time_counter + 1;
         if valid_trigger_int = '1' then
           valid_trigger_counter_t <= valid_trigger_counter_t + 1;
-        elsif LVL1_INVALID_TRG_IN = '1' or (trigger_busy_int = '1' and  TIMING_TRIGGER_IN ='1') then
+        elsif LVL1_INVALID_TRG_IN = '1' or (trigger_busy_int = '1' and  timing_trigger_edge = "01") then
           invalid_trigger_counter_t <= invalid_trigger_counter_t + 1;
         end if;
       else