---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_sync_down is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); --select slave mode
- port(
- OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
- LINK_PHASE_OUT : out std_logic := '0'; --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-
-architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture is "media_downlink_group";
- attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
-generic
- (
-DCSMODE : string :=“POS”
-);
--- synthesis translate_on
-port (
- CLK0 :in std_logic ;
- CLK1 :in std_logic ;
- SEL :in std_logic ;
- DCSOUT :out std_logic) ;
-end component;
-
-
---signal clk_200_i : std_logic;
---signal clk_200_internal : std_logic;
-signal clk_200_osc : std_logic;
-signal clk_100_osc : std_logic;
-signal rx_full_clk_ch0 : std_logic;
-signal rx_half_clk_ch0 : std_logic;
-signal tx_full_clk_ch0 : std_logic;
-signal tx_half_clk_ch0 : std_logic;
-
-signal tx_data : std_logic_vector(7 downto 0);
-signal tx_k : std_logic;
-signal rx_data : std_logic_vector(7 downto 0);
-signal rx_k : std_logic;
-signal rx_error : std_logic;
-
-signal rst_n : std_logic;
-signal rst : std_logic; -- PL!
-signal rx_serdes_rst : std_logic;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : std_logic;
-signal rx_pcs_rst : std_logic;
-signal rst_qd : std_logic;
-signal serdes_rst_qd : std_logic;
-signal sd_los_i : std_logic; --PL!
-
-signal rx_los_low : std_logic;
-signal lsm_status : std_logic;
-signal rx_cdr_lol : std_logic;
-signal tx_pll_lol : std_logic;
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;--
-attribute syn_keep : boolean;--
-attribute syn_preserve of sci_ch_i : signal is true;--
-attribute syn_keep of sci_ch_i : signal is true;--
-attribute syn_preserve of sci_qd_i : signal is true;--
-attribute syn_keep of sci_qd_i : signal is true;--
-attribute syn_preserve of sci_reg_i : signal is true;--
-attribute syn_keep of sci_reg_i : signal is true;--
-attribute syn_preserve of sci_addr_i : signal is true;--
-attribute syn_keep of sci_addr_i : signal is true;--
-attribute syn_preserve of sci_data_in_i : signal is true;--
-attribute syn_keep of sci_data_in_i : signal is true;--
-attribute syn_preserve of sci_data_out_i : signal is true;--
-attribute syn_keep of sci_data_out_i : signal is true;--
-attribute syn_preserve of sci_read_i : signal is true;--
-attribute syn_keep of sci_read_i : signal is true;--
-attribute syn_preserve of sci_write_i : signal is true;--
-attribute syn_keep of sci_write_i : signal is true;--
-attribute syn_preserve of sci_write_shift_i : signal is true;--
-attribute syn_keep of sci_write_shift_i : signal is true;--
-attribute syn_preserve of sci_read_shift_i : signal is true;--
-attribute syn_keep of sci_read_shift_i : signal is true;--
-
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : std_logic;
-signal rx_allow : std_logic;
-signal tx_allow_q : std_logic;
-signal rx_allow_q : std_logic;
-signal link_phase_S : std_logic; --PL!
-signal request_retr_i : std_logic;
-signal start_retr_i : std_logic;
-signal request_retr_position_i : std_logic_vector(7 downto 0);
-signal start_retr_position_i : std_logic_vector(7 downto 0);
-signal send_link_reset_i : std_logic;
-signal make_link_reset_i : std_logic;
-signal got_link_ready_i : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve of wa_position : signal is true;--
-attribute syn_keep of wa_position : signal is true;--
-attribute syn_preserve of wa_position_rx : signal is true;--
-attribute syn_keep of wa_position_rx : signal is true;--
-
-signal stat_rx_control_i : std_logic_vector(31 downto 0);
-signal stat_tx_control_i : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state : std_logic_vector(3 downto 0);
-signal tx_fsm_state : std_logic_vector(3 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : unsigned(12 downto 0) := (others => '0');
-signal start_timer : unsigned(18 downto 0) := (others => '0');
---signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
---signal watchdog_trigger : std_logic :='0';
-
-begin
-
-clk_200_osc <= OSCCLK;
-clk_100_osc <= SYSCLK;
-
-RX_HALF_CLK_OUT <= rx_half_clk_ch0;
-RX_FULL_CLK_OUT <= rx_full_clk_ch0;
-TX_HALF_CLK_OUT <= tx_half_clk_ch0;
-TX_FULL_CLK_OUT <= tx_full_clk_ch0;
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-
---rst_n <= not CLEAR; PL!
---rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);
---rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);
-rst_n <= not(CLEAR or internal_make_link_reset_out);
-rst <= (CLEAR or internal_make_link_reset_out);
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_sync_source_downstream
- port map(
- hdinp_ch0 => SD_RXD_P_IN,
- hdinn_ch0 => SD_RXD_N_IN,
- hdoutp_ch0 => SD_TXD_P_OUT,
- hdoutn_ch0 => SD_TXD_N_OUT,
- rxiclk_ch0 => tx_full_clk_ch0, -- read fifo is no longer present! PL!
- txiclk_ch0 => tx_full_clk_ch0,
- rx_full_clk_ch0 => rx_full_clk_ch0,
- rx_half_clk_ch0 => rx_half_clk_ch0,
- tx_full_clk_ch0 => tx_full_clk_ch0,
- tx_half_clk_ch0 => tx_half_clk_ch0,
- fpga_rxrefclk_ch0 => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT
- txdata_ch0 => tx_data,
- tx_k_ch0 => tx_k,
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data,
- rx_k_ch0 => rx_k,
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error,
- rx_serdes_rst_ch0_c => rx_serdes_rst,
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst,
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst,
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low,
- lsm_status_ch0_s => lsm_status,
- rx_cdr_lol_ch0_s => rx_cdr_lol,
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
- refclk2fpga => open, --refclk2core_S,
-
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_CH0 => sci_ch_i(0),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
-
- fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT
- tx_serdes_rst_c => tx_serdes_rst,
- tx_pll_lol_qd_s => tx_pll_lol,
- rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
-
- );
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => clk_200_osc, --rx_full_clk_ch0,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RX_SERDES_RST_CH_C => rx_serdes_rst,
- RX_CDR_LOL_CH_S => rx_cdr_lol,
- RX_LOS_LOW_CH_S => rx_los_low,
- RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(3 downto 0),
- STATE_OUT => rx_fsm_state
- );
-
-THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n,
- TX_REFCLK => clk_200_osc,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RST_QD_C => rst_qd,
- TX_PCS_RST_CH_C => tx_pcs_rst,
- STATE_OUT => tx_fsm_state
- );
-
--- Master does not do bit-locking
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
- wait until rising_edge(clk_200_osc); --clk_200_i);
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- rx_allow <= '1';
- else
- rx_allow <= '0';
- end if;
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- tx_allow <= '1';
- else
- tx_allow <= '0';
- end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(clk_100_osc);
-tx_allow_q <= tx_allow when rising_edge(clk_100_osc);
-
-\r
--- start_timer begins when the rx-link is ready; i.e.: there is a working link.
--- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high.
--- This gives a slave on the other side time to start-up
--- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset
-PROC_START_TIMER : process(clk_200_osc) --clk_200_i)
-begin
- if rising_edge(clk_200_osc) then
- if got_link_ready_i = '1' then
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- end if;
- end if;
+--Media interface for Lattice ECP3 using PCS at 2GHz\r
+\r
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.med_sync_define.all;\r
+use work.soda_components.all;\r
+\r
+entity med_ecp3_sfp_sync_down is\r
+ generic( SERDES_NUM : integer range 0 to 3 := 0;\r
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode\r
+ port(\r
+ OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock\r
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ --Internal Connection TX\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic := '0';\r
+ --Internal Connection RX\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');\r
+ MED_DATAREADY_OUT : out std_logic := '0';\r
+ MED_READ_IN : in std_logic;\r
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
+ TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz\r
+ TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz\r
+\r
+ --Sync operation\r
+ RX_DLM : out std_logic := '0';\r
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM : in std_logic := '0';\r
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!\r
+\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic; --not used\r
+ SD_REFCLK_N_IN : in std_logic; --not used\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ SCI_NACK : out std_logic := '0';\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')\r
+ );\r
+end entity;\r
+\r
+\r
+architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture is "media_downlink_group";\r
+ attribute syn_sharing : string;\r
+ attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";\r
+\r
+\r
+component DCS\r
+-- synthesis translate_off\r
+generic\r
+ (\r
+DCSMODE : string :=“POS”\r
+);\r
+-- synthesis translate_on\r
+port (\r
+ CLK0 :in std_logic ;\r
+ CLK1 :in std_logic ;\r
+ SEL :in std_logic ;\r
+ DCSOUT :out std_logic) ;\r
+end component;\r
+\r
+\r
+--signal clk_200_i : std_logic;\r
+--signal clk_200_internal : std_logic;\r
+signal clk_200_osc : std_logic;\r
+signal clk_100_osc : std_logic;\r
+signal rx_full_clk_ch0 : std_logic;\r
+signal rx_half_clk_ch0 : std_logic;\r
+signal tx_full_clk_ch0 : std_logic;\r
+signal tx_half_clk_ch0 : std_logic;\r
+\r
+signal tx_data : std_logic_vector(7 downto 0);\r
+signal tx_k : std_logic;\r
+signal rx_data : std_logic_vector(7 downto 0);\r
+signal rx_k : std_logic;\r
+signal rx_error : std_logic;\r
+\r
+signal rst_n : std_logic;\r
+signal rst : std_logic; -- PL!\r
+signal rx_serdes_rst : std_logic;\r
+signal tx_serdes_rst : std_logic;\r
+signal tx_pcs_rst : std_logic;\r
+signal rx_pcs_rst : std_logic;\r
+signal rst_qd : std_logic;\r
+signal serdes_rst_qd : std_logic;\r
+signal sd_los_i : std_logic; --PL!\r
+\r
+signal rx_los_low : std_logic;\r
+signal lsm_status : std_logic;\r
+signal rx_cdr_lol : std_logic;\r
+signal tx_pll_lol : std_logic;\r
+\r
+signal sci_ch_i : std_logic_vector(3 downto 0);\r
+signal sci_qd_i : std_logic;\r
+signal sci_reg_i : std_logic;\r
+signal sci_addr_i : std_logic_vector(8 downto 0);\r
+signal sci_data_in_i : std_logic_vector(7 downto 0);\r
+signal sci_data_out_i : std_logic_vector(7 downto 0);\r
+signal sci_read_i : std_logic;\r
+signal sci_write_i : std_logic;\r
+signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
+signal sci_read_shift_i : std_logic_vector(2 downto 0);\r
+\r
+-- fix signal names for constraining\r
+attribute syn_preserve : boolean;--\r
+attribute syn_keep : boolean;--\r
+attribute syn_preserve of sci_ch_i : signal is true;--\r
+attribute syn_keep of sci_ch_i : signal is true;--\r
+attribute syn_preserve of sci_qd_i : signal is true;--\r
+attribute syn_keep of sci_qd_i : signal is true;--\r
+attribute syn_preserve of sci_reg_i : signal is true;--\r
+attribute syn_keep of sci_reg_i : signal is true;--\r
+attribute syn_preserve of sci_addr_i : signal is true;--\r
+attribute syn_keep of sci_addr_i : signal is true;--\r
+attribute syn_preserve of sci_data_in_i : signal is true;--\r
+attribute syn_keep of sci_data_in_i : signal is true;--\r
+attribute syn_preserve of sci_data_out_i : signal is true;--\r
+attribute syn_keep of sci_data_out_i : signal is true;--\r
+attribute syn_preserve of sci_read_i : signal is true;--\r
+attribute syn_keep of sci_read_i : signal is true;--\r
+attribute syn_preserve of sci_write_i : signal is true;--\r
+attribute syn_keep of sci_write_i : signal is true;--\r
+attribute syn_preserve of sci_write_shift_i : signal is true;--\r
+attribute syn_keep of sci_write_shift_i : signal is true;--\r
+attribute syn_preserve of sci_read_shift_i : signal is true;--\r
+attribute syn_keep of sci_read_shift_i : signal is true;--\r
+\r
+signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
+signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
+signal tx_allow : std_logic;\r
+signal rx_allow : std_logic;\r
+signal tx_allow_q : std_logic;\r
+signal rx_allow_q : std_logic;\r
+signal link_phase_S : std_logic; --PL!\r
+signal request_retr_i : std_logic;\r
+signal start_retr_i : std_logic;\r
+signal request_retr_position_i : std_logic_vector(7 downto 0);\r
+signal start_retr_position_i : std_logic_vector(7 downto 0);\r
+signal send_link_reset_i : std_logic;\r
+signal make_link_reset_i : std_logic;\r
+signal got_link_ready_i : std_logic;\r
+signal internal_make_link_reset_out : std_logic;\r
+\r
+attribute syn_preserve of wa_position : signal is true;--\r
+attribute syn_keep of wa_position : signal is true;--\r
+attribute syn_preserve of wa_position_rx : signal is true;--\r
+attribute syn_keep of wa_position_rx : signal is true;--\r
+\r
+signal stat_rx_control_i : std_logic_vector(31 downto 0);\r
+signal stat_tx_control_i : std_logic_vector(31 downto 0);\r
+signal debug_rx_control_i : std_logic_vector(31 downto 0);\r
+signal debug_tx_control_i : std_logic_vector(31 downto 0);\r
+signal rx_fsm_state : std_logic_vector(3 downto 0);\r
+signal tx_fsm_state : std_logic_vector(3 downto 0);\r
+signal debug_reg : std_logic_vector(63 downto 0);\r
+\r
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
+signal sci_state : sci_ctrl;\r
+signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
+signal start_timer : unsigned(18 downto 0) := (others => '0');\r
+--signal watchdog_timer : unsigned(20 downto 0) := (others => '0');\r
+--signal watchdog_trigger : std_logic :='0';\r
+\r
+begin\r
+\r
+clk_200_osc <= OSCCLK; \r
+clk_100_osc <= SYSCLK; \r
+ \r
+RX_HALF_CLK_OUT <= rx_half_clk_ch0;\r
+RX_FULL_CLK_OUT <= rx_full_clk_ch0;\r
+TX_HALF_CLK_OUT <= tx_half_clk_ch0;\r
+TX_FULL_CLK_OUT <= tx_full_clk_ch0;\r
+\r
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready\r
+\r
+\r
+--rst_n <= not CLEAR; PL!\r
+--rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);\r
+--rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);\r
+rst_n <= not(CLEAR or internal_make_link_reset_out);\r
+rst <= (CLEAR or internal_make_link_reset_out);\r
+\r
+------------------------------------------------- \r
+-- Serdes\r
+------------------------------------------------- \r
+THE_SERDES : entity work.serdes_sync_source_downstream\r
+ port map(\r
+ hdinp_ch0 => SD_RXD_P_IN,\r
+ hdinn_ch0 => SD_RXD_N_IN,\r
+ hdoutp_ch0 => SD_TXD_P_OUT,\r
+ hdoutn_ch0 => SD_TXD_N_OUT,\r
+ rxiclk_ch0 => tx_full_clk_ch0, -- read fifo is no longer present! PL!\r
+ txiclk_ch0 => tx_full_clk_ch0,\r
+ rx_full_clk_ch0 => rx_full_clk_ch0,\r
+ rx_half_clk_ch0 => rx_half_clk_ch0,\r
+ tx_full_clk_ch0 => tx_full_clk_ch0,\r
+ tx_half_clk_ch0 => tx_half_clk_ch0,\r
+ fpga_rxrefclk_ch0 => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT\r
+ txdata_ch0 => tx_data,\r
+ tx_k_ch0 => tx_k,\r
+ tx_force_disp_ch0 => '0',\r
+ tx_disp_sel_ch0 => '0',\r
+ rxdata_ch0 => rx_data,\r
+ rx_k_ch0 => rx_k,\r
+ rx_disp_err_ch0 => open,\r
+ rx_cv_err_ch0 => rx_error,\r
+ rx_serdes_rst_ch0_c => rx_serdes_rst,\r
+ sb_felb_ch0_c => '0',\r
+ sb_felb_rst_ch0_c => '0',\r
+ tx_pcs_rst_ch0_c => tx_pcs_rst,\r
+ tx_pwrup_ch0_c => '1',\r
+ rx_pcs_rst_ch0_c => rx_pcs_rst,\r
+ rx_pwrup_ch0_c => '1',\r
+ rx_los_low_ch0_s => rx_los_low,\r
+ lsm_status_ch0_s => lsm_status,\r
+ rx_cdr_lol_ch0_s => rx_cdr_lol,\r
+ tx_div2_mode_ch0_c => '0',\r
+ rx_div2_mode_ch0_c => '0',\r
+ refclk2fpga => open, --refclk2core_S,\r
+ \r
+ SCI_WRDATA => sci_data_in_i,\r
+ SCI_RDDATA => sci_data_out_i,\r
+ SCI_ADDR => sci_addr_i(5 downto 0),\r
+ SCI_SEL_QUAD => sci_qd_i,\r
+ SCI_SEL_CH0 => sci_ch_i(0),\r
+ SCI_RD => sci_read_i,\r
+ SCI_WRN => sci_write_i,\r
+ \r
+ fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT\r
+ tx_serdes_rst_c => tx_serdes_rst,\r
+ tx_pll_lol_qd_s => tx_pll_lol,\r
+ rst_qd_c => rst_qd,\r
+ serdes_rst_qd_c => serdes_rst_qd\r
+\r
+ );\r
+\r
+------------------------------------------------- \r
+-- Reset FSM & Link states\r
+------------------------------------------------- \r
+THE_RX_FSM : rx_reset_fsm\r
+ port map(\r
+ RST_N => rst_n,\r
+ RX_REFCLK => clk_200_osc, --rx_full_clk_ch0,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol,\r
+ RX_SERDES_RST_CH_C => rx_serdes_rst,\r
+ RX_CDR_LOL_CH_S => rx_cdr_lol,\r
+ RX_LOS_LOW_CH_S => rx_los_low,\r
+ RX_PCS_RST_CH_C => rx_pcs_rst,\r
+ WA_POSITION => wa_position_rx(3 downto 0),\r
+ STATE_OUT => rx_fsm_state\r
+ );\r
+ \r
+THE_TX_FSM : tx_reset_fsm\r
+ port map(\r
+ RST_N => rst_n,\r
+ TX_REFCLK => clk_200_osc,\r
+ TX_PLL_LOL_QD_S => tx_pll_lol,\r
+ RST_QD_C => rst_qd,\r
+ TX_PCS_RST_CH_C => tx_pcs_rst,\r
+ STATE_OUT => tx_fsm_state\r
+ );\r
+\r
+-- Master does not do bit-locking \r
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";\r
+\r
+\r
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable\r
+PROC_ALLOW : process begin\r
+ wait until rising_edge(clk_200_osc); --clk_200_i);\r
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
+ rx_allow <= '1';\r
+ else\r
+ rx_allow <= '0';\r
+ end if;\r
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
+ tx_allow <= '1';\r
+ else\r
+ tx_allow <= '0';\r
+ end if;\r
+end process;\r
+\r
+rx_allow_q <= rx_allow when rising_edge(clk_100_osc);\r
+tx_allow_q <= tx_allow when rising_edge(clk_100_osc);\r
+\r
+\r
+-- start_timer begins when the rx-link is ready; i.e.: there is a working link.\r
+-- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high.\r
+-- This gives a slave on the other side time to start-up\r
+-- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset\r
+PROC_START_TIMER : process(clk_200_osc) --clk_200_i)\r
+begin\r
+ if rising_edge(clk_200_osc) then\r
+ if got_link_ready_i = '1' then\r
+ if start_timer(start_timer'left) = '0' then\r
+ start_timer <= start_timer + 1;\r
+ end if; \r
+ else\r
+ start_timer <= (others => '0');\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+------------------------------------------------- \r
+-- TX Data\r
+------------------------------------------------- \r
+THE_TX : soda_tx_control\r
+ port map(\r
+ CLK_200 => clk_200_osc,\r
+ CLK_100 => clk_100_osc,\r
+ RESET_IN => rst, --CLEAR, PL!\r
+\r
+ TX_DATA_IN => MED_DATA_IN,\r
+ TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,\r
+ TX_WRITE_IN => MED_DATAREADY_IN,\r
+ TX_READ_OUT => MED_READ_OUT,\r
+\r
+ TX_DATA_OUT => tx_data,\r
+ TX_K_OUT => tx_k,\r
+\r
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO\r
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO\r
+\r
+ START_RETRANSMIT_IN => start_retr_i, --TODO\r
+ START_POSITION_IN => request_retr_position_i, --TODO\r
+\r
+ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,\r
+ SEND_DLM => TX_DLM,\r
+ SEND_DLM_WORD => TX_DLM_WORD,\r
+\r
+ SEND_LINK_RESET_IN => CTRL_OP(15),\r
+ TX_ALLOW_IN => tx_allow,\r
+ RX_ALLOW_IN => rx_allow,\r
+ LINK_PHASE_OUT => link_phase_S, --PL!\r
+\r
+ DEBUG_OUT => debug_tx_control_i,\r
+ STAT_REG_OUT => stat_tx_control_i\r
+); \r
+\r
+LINK_PHASE_OUT <= link_phase_S; --PL!\r
+------------------------------------------------- \r
+-- RX Data\r
+------------------------------------------------- \r
+THE_RX_CONTROL : rx_control\r
+ port map(\r
+ CLK_200 => clk_200_osc, --rx_full_clk_ch0, PL! 270814\r
+ CLK_100 => clk_100_osc,\r
+ RESET_IN => rst, --CLEAR, PL!\r
+\r
+ RX_DATA_OUT => MED_DATA_OUT,\r
+ RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,\r
+ RX_WRITE_OUT => MED_DATAREADY_OUT,\r
+ RX_READ_IN => MED_READ_IN,\r
+\r
+ RX_DATA_IN => rx_data,\r
+ RX_K_IN => rx_k,\r
+\r
+ REQUEST_RETRANSMIT_OUT => request_retr_i,\r
+ REQUEST_POSITION_OUT => request_retr_position_i,\r
+\r
+ START_RETRANSMIT_OUT => start_retr_i,\r
+ START_POSITION_OUT => start_retr_position_i,\r
+\r
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
+ RX_DLM => RX_DLM,\r
+ RX_DLM_WORD => RX_DLM_WORD,\r
+ \r
+ SEND_LINK_RESET_OUT => send_link_reset_i,\r
+ MAKE_RESET_OUT => make_link_reset_i,\r
+ RX_ALLOW_IN => rx_allow,\r
+ GOT_LINK_READY => got_link_ready_i,\r
+\r
+ DEBUG_OUT => debug_rx_control_i,\r
+ STAT_REG_OUT => stat_rx_control_i\r
+ ); \r
+ \r
+ \r
+ \r
+------------------------------------------------- \r
+-- SCI\r
+------------------------------------------------- \r
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
+PROC_SCI_CTRL: process \r
+ variable cnt : integer range 0 to 4 := 0;\r
+begin\r
+ wait until rising_edge(clk_100_osc);\r
+ SCI_ACK <= '0';\r
+ case sci_state is\r
+ when IDLE =>\r
+ sci_ch_i <= x"0";\r
+ sci_qd_i <= '0';\r
+ sci_reg_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_write_i <= '0';\r
+ sci_timer <= sci_timer + 1;\r
+ if SCI_READ = '1' or SCI_WRITE = '1' then\r
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_addr_i <= SCI_ADDR;\r
+ sci_data_in_i <= SCI_DATA_IN;\r
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_state <= SCTRL;\r
+ elsif sci_timer(sci_timer'left) = '1' then\r
+ sci_timer <= (others => '0');\r
+ sci_state <= GET_WA;\r
+ end if; \r
+ when SCTRL =>\r
+ if sci_reg_i = '1' then\r
+ SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= SCTRL_WAIT;\r
+ end if;\r
+ when SCTRL_WAIT =>\r
+ sci_state <= SCTRL_WAIT2;\r
+ when SCTRL_WAIT2 =>\r
+ sci_state <= SCTRL_FINISH;\r
+ when SCTRL_FINISH =>\r
+ SCI_DATA_OUT <= sci_data_out_i;\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ \r
+ when GET_WA =>\r
+ if cnt = 4 then\r
+ cnt := 0;\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= GET_WA_WAIT;\r
+ sci_addr_i <= '0' & x"22";\r
+ sci_ch_i <= x"0";\r
+ sci_ch_i(cnt) <= '1';\r
+ sci_read_i <= '1';\r
+ end if;\r
+ when GET_WA_WAIT =>\r
+ sci_state <= GET_WA_WAIT2;\r
+ when GET_WA_WAIT2 =>\r
+ sci_state <= GET_WA_FINISH;\r
+ when GET_WA_FINISH =>\r
+ wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
+ sci_state <= GET_WA; \r
+ cnt := cnt + 1;\r
+ end case;\r
+ \r
+ if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
+ SCI_NACK <= '1';\r
+ else\r
+ SCI_NACK <= '0';\r
+ end if;\r
+ \r
end process;\r
-
--------------------------------------------------
--- TX Data
--------------------------------------------------
-THE_TX : soda_tx_control
- port map(
- CLK_200 => clk_200_osc,
- CLK_100 => clk_100_osc,
- RESET_IN => rst, --CLEAR, PL!
-
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
-
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
-
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
-
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => request_retr_position_i, --TODO
-
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
-
- SEND_LINK_RESET_IN => CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
- LINK_PHASE_OUT => link_phase_S, --PL!
-
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
-);
-
-LINK_PHASE_OUT <= link_phase_S; --PL!
--------------------------------------------------
--- RX Data
--------------------------------------------------
-THE_RX_CONTROL : rx_control
- port map(
- CLK_200 => clk_200_osc, --rx_full_clk_ch0, PL! 270814
- CLK_100 => clk_100_osc,
- RESET_IN => rst, --CLEAR, PL!
-
- RX_DATA_OUT => MED_DATA_OUT,
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
- RX_WRITE_OUT => MED_DATAREADY_OUT,
- RX_READ_IN => MED_READ_IN,
-
- RX_DATA_IN => rx_data,
- RX_K_IN => rx_k,
-
- REQUEST_RETRANSMIT_OUT => request_retr_i,
- REQUEST_POSITION_OUT => request_retr_position_i,
-
- START_RETRANSMIT_OUT => start_retr_i,
- START_POSITION_OUT => start_retr_position_i,
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => RX_DLM,
- RX_DLM_WORD => RX_DLM_WORD,
-
- SEND_LINK_RESET_OUT => send_link_reset_i,
- MAKE_RESET_OUT => make_link_reset_i,
- RX_ALLOW_IN => rx_allow,
- GOT_LINK_READY => got_link_ready_i,
-
- DEBUG_OUT => debug_rx_control_i,
- STAT_REG_OUT => stat_rx_control_i
- );
-
-
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
- variable cnt : integer range 0 to 4 := 0;
-begin
- wait until rising_edge(clk_100_osc);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
-
-end process;
-
-
--------------------------------------------------
--- Debug Registers
--------------------------------------------------
-debug_reg(3 downto 0) <= rx_fsm_state;
-debug_reg(4) <= rx_k;
-debug_reg(5) <= rx_error;
-debug_reg(6) <= rx_los_low;
-debug_reg(7) <= rx_cdr_lol;
-
-debug_reg(8) <= tx_k;
-debug_reg(9) <= tx_pll_lol;
-debug_reg(10) <= lsm_status;
-debug_reg(11) <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data;
-
-debug_reg(16) <= '0';
-debug_reg(17) <= tx_allow;
-debug_reg(18) <= RESET;
-debug_reg(19) <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36) <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-
-STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc); -- PL!
-
-STAT_OP(15) <= send_link_reset_i when rising_edge(clk_100_osc);
-STAT_OP(14) <= '0';
-STAT_OP(13) <= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset
-STAT_OP(12) <= '0';
-STAT_OP(11) <= '0';
-STAT_OP(10) <= rx_allow;
-STAT_OP(9) <= tx_allow;
---STAT_OP(8 downto 4) <= (others => '0');
-STAT_OP(8) <= got_link_ready_i;
-STAT_OP(7) <= send_link_reset_i;
-STAT_OP(6) <= make_link_reset_i;
-STAT_OP(5) <= request_retr_i;
-STAT_OP(4) <= start_retr_i;
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
+\r
+\r
+------------------------------------------------- \r
+-- Debug Registers\r
+------------------------------------------------- \r
+debug_reg(3 downto 0) <= rx_fsm_state;\r
+debug_reg(4) <= rx_k;\r
+debug_reg(5) <= rx_error;\r
+debug_reg(6) <= rx_los_low;\r
+debug_reg(7) <= rx_cdr_lol;\r
+\r
+debug_reg(8) <= tx_k;\r
+debug_reg(9) <= tx_pll_lol;\r
+debug_reg(10) <= lsm_status;\r
+debug_reg(11) <= make_link_reset_i;\r
+debug_reg(15 downto 12) <= tx_fsm_state;\r
+-- debug_reg(31 downto 24) <= tx_data; \r
+\r
+debug_reg(16) <= '0';\r
+debug_reg(17) <= tx_allow;\r
+debug_reg(18) <= RESET;\r
+debug_reg(19) <= CLEAR;\r
+debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);\r
+\r
+debug_reg(35 downto 32) <= wa_position(3 downto 0);\r
+debug_reg(36) <= debug_tx_control_i(6);\r
+debug_reg(39 downto 37) <= "000";\r
+debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);\r
+\r
+ \r
+STAT_DEBUG <= debug_reg;\r
+\r
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';\r
+sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc); -- PL!\r
+\r
+STAT_OP(15) <= send_link_reset_i when rising_edge(clk_100_osc);\r
+STAT_OP(14) <= '0';\r
+STAT_OP(13) <= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset\r
+STAT_OP(12) <= '0';\r
+STAT_OP(11) <= '0';\r
+STAT_OP(10) <= rx_allow;\r
+STAT_OP(9) <= tx_allow;\r
+--STAT_OP(8 downto 4) <= (others => '0');\r
+STAT_OP(8) <= got_link_ready_i;\r
+STAT_OP(7) <= send_link_reset_i;\r
+STAT_OP(6) <= make_link_reset_i;\r
+STAT_OP(5) <= request_retr_i;\r
+STAT_OP(4) <= start_retr_i;\r
+STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";\r
\r
end med_ecp3_sfp_sync_down_arch;
\ No newline at end of file
+++ /dev/null
-rvl_alias "rxup_full_clk" "rxup_full_clk";\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-BLOCK RD_DURING_WR_PATHS ;\r
-BLOCK JTAGPATHS ;\r
-#################################################################\r
-# Basic Settings\r
-#################################################################\r
-SYSCONFIG MCCLK_FREQ = 20;\r
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
-#################################################################\r
-# Clock I/O\r
-#################################################################\r
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# To central FPGA\r
-#################################################################\r
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;\r
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;\r
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;\r
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;\r
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;\r
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;\r
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;\r
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;\r
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;\r
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;\r
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;\r
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;\r
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;\r
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;\r
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;\r
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;\r
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;\r
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;\r
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;\r
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;\r
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;\r
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;\r
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;\r
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;\r
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;\r
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;\r
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;\r
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;\r
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
-#################################################################\r
-# Connection to AddOn\r
-#################################################################\r
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1\r
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3\r
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5\r
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7\r
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15\r
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17\r
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21\r
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23\r
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25\r
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27\r
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35\r
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2\r
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4\r
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6\r
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8\r
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18\r
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22\r
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24\r
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26\r
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28\r
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36\r
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38\r
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169\r
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171\r
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173\r
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175\r
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183\r
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185\r
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170\r
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172\r
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174\r
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176\r
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184\r
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186\r
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
-DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#################################################################\r
-# Additional Lines to AddOn\r
-#################################################################\r
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
-#all lines are input only\r
-#line 4/5 go to PLL input\r
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 \r
-#################################################################\r
-# Flash ROM and Reboot\r
-#################################################################\r
-LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
-LOCATE COMP "FLASH_CS" SITE "E11" ;\r
-LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
-LOCATE COMP "PROGRAMN" SITE "B11" ;\r
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#################################################################\r
-# Misc\r
-#################################################################\r
-LOCATE COMP "TEMPSENS" SITE "A13" ;\r
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#coding of FPGA number\r
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;\r
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;\r
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#terminated differential pair to pads\r
-LOCATE COMP "SUPPL" SITE "C14" ;\r
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# LED\r
-#################################################################\r
-LOCATE COMP "LED_GREEN" SITE "F12" ;\r
-LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
-LOCATE COMP "LED_RED" SITE "A15" ;\r
-LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
-DEFINE PORT GROUP "LED_group" "LED*" ;\r
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
-\r
-\r
-#################################################################\r
-#GSR_NET NET "GSR_N"; \r
-#################################################################\r
-# Locate Serdes and media interfaces\r
-#################################################################\r
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
-\r
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
-\r
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
-\r
-#UGROUP "SPIlogic" BBOX 20 20\r
-# BLKNAME THE_SPI_RELOAD;\r
-#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
-\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]";\r
-\r
-## IOBUF ALLPORTS ;\r
-USE PRIMARY NET "clk_200_osc" ;\r
-USE PRIMARY NET "clk_100_osc" ;\r
-USE PRIMARY NET "rxup_full_clk" ;\r
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
--- /dev/null
+rvl_alias "rxup_full_clk" "rxup_full_clk";\r
+BLOCK RESETPATHS ;\r
+BLOCK ASYNCPATHS ;\r
+BLOCK RD_DURING_WR_PATHS ;\r
+BLOCK JTAGPATHS ;\r
+\r
+#################################################################\r
+# Basic Settings\r
+#################################################################\r
+SYSCONFIG MCCLK_FREQ = 20;\r
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
+\r
+#################################################################\r
+# Clock I/O\r
+#################################################################\r
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
+#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
+#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
+#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
+#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
+#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
+DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
+\r
+#################################################################\r
+# To central FPGA\r
+#################################################################\r
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;\r
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;\r
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;\r
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;\r
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;\r
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;\r
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;\r
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;\r
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;\r
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;\r
+LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;\r
+LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;\r
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+\r
+LOCATE COMP "TEST_LINE_0" SITE "A5" ;\r
+LOCATE COMP "TEST_LINE_1" SITE "A6" ;\r
+LOCATE COMP "TEST_LINE_2" SITE "G8" ;\r
+LOCATE COMP "TEST_LINE_3" SITE "F9" ;\r
+LOCATE COMP "TEST_LINE_4" SITE "D9" ;\r
+LOCATE COMP "TEST_LINE_5" SITE "D10" ;\r
+LOCATE COMP "TEST_LINE_6" SITE "F10" ;\r
+LOCATE COMP "TEST_LINE_7" SITE "E10" ;\r
+LOCATE COMP "TEST_LINE_8" SITE "A8" ;\r
+LOCATE COMP "TEST_LINE_9" SITE "B8" ;\r
+LOCATE COMP "TEST_LINE_10" SITE "G10" ;\r
+LOCATE COMP "TEST_LINE_11" SITE "G9" ;\r
+LOCATE COMP "TEST_LINE_12" SITE "C9" ;\r
+LOCATE COMP "TEST_LINE_13" SITE "C10" ;\r
+LOCATE COMP "TEST_LINE_14" SITE "H10" ;\r
+LOCATE COMP "TEST_LINE_15" SITE "H11" ;\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
+\r
+#################################################################\r
+# Connection to AddOn\r
+#################################################################\r
+LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1\r
+LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3\r
+LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5\r
+LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7\r
+#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
+#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
+#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
+LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15\r
+LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17\r
+#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
+LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21\r
+LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23\r
+LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25\r
+LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27\r
+#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
+#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
+#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35\r
+LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
+#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
+LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2\r
+LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4\r
+LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6\r
+LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8\r
+#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
+#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
+#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
+LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18\r
+#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
+LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22\r
+LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24\r
+LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26\r
+LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28\r
+#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
+#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
+#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
+LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36\r
+LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38\r
+#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
+LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169\r
+LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171\r
+LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173\r
+LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175\r
+#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
+#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
+#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
+LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183\r
+LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185\r
+#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
+LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170\r
+LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172\r
+LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174\r
+LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176\r
+#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
+#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
+#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
+LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184\r
+LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186\r
+#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
+\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+ \r
+#################################################################\r
+# Additional Lines to AddOn\r
+#################################################################\r
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
+#all lines are input only\r
+#line 4/5 go to PLL input\r
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71\r
+\r
+#################################################################\r
+# Flash ROM and Reboot\r
+#################################################################\r
+LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
+LOCATE COMP "FLASH_CS" SITE "E11" ;\r
+LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
+LOCATE COMP "PROGRAMN" SITE "B11" ;\r
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+\r
+#################################################################\r
+# Misc\r
+#################################################################\r
+LOCATE COMP "TEMPSENS" SITE "A13" ;\r
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+#coding of FPGA number\r
+LOCATE COMP "CODE_LINE_1" SITE "AA20" ;\r
+LOCATE COMP "CODE_LINE_0" SITE "Y21" ;\r
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#terminated differential pair to pads\r
+LOCATE COMP "SUPPL" SITE "C14" ;\r
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
+\r
+#################################################################\r
+# LED\r
+#################################################################\r
+LOCATE COMP "LED_GREEN" SITE "F12" ;\r
+LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
+LOCATE COMP "LED_RED" SITE "A15" ;\r
+LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
+DEFINE PORT GROUP "LED_group" "LED*" ;\r
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
+\r
+\r
+#################################################################\r
+#GSR_NET NET "GSR_N"; \r
+#################################################################\r
+# Locate Serdes and media interfaces\r
+#################################################################\r
+LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
+\r
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
+#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
+\r
+BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
+\r
+#UGROUP "SPIlogic" BBOX 20 20\r
+# BLKNAME THE_SPI_RELOAD;\r
+#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
+\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";\r
+\r
+## IOBUF ALLPORTS ;\r
+USE PRIMARY NET "clk_200_osc" ;\r
+USE PRIMARY NET "clk_100_osc" ;\r
+USE PRIMARY NET "rxup_full_clk" ;\r
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
+FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
--- /dev/null
+rvl_alias "rxup_full_clk" "rxup_full_clk";\r
+BLOCK RESETPATHS ;\r
+BLOCK ASYNCPATHS ;\r
+BLOCK RD_DURING_WR_PATHS ;\r
+BLOCK JTAGPATHS ;\r
+#################################################################\r
+# Basic Settings\r
+#################################################################\r
+SYSCONFIG MCCLK_FREQ = 20;\r
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
+#################################################################\r
+# Clock I/O\r
+#################################################################\r
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
+#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
+#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
+#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
+#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
+#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
+DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
+#################################################################\r
+# To central FPGA\r
+#################################################################\r
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;\r
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;\r
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;\r
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;\r
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;\r
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;\r
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;\r
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;\r
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;\r
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;\r
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;\r
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;\r
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;\r
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;\r
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;\r
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;\r
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;\r
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;\r
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;\r
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;\r
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;\r
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;\r
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;\r
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;\r
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;\r
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;\r
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;\r
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
+#################################################################\r
+# Connection to AddOn\r
+#################################################################\r
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1\r
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3\r
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5\r
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7\r
+#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
+#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
+#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15\r
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17\r
+#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21\r
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23\r
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25\r
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27\r
+#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
+#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
+#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35\r
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
+#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2\r
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4\r
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6\r
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8\r
+#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
+#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
+#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18\r
+#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22\r
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24\r
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26\r
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28\r
+#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
+#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
+#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36\r
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38\r
+#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169\r
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171\r
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173\r
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175\r
+#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
+#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
+#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183\r
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185\r
+#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170\r
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172\r
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174\r
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176\r
+#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
+#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
+#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184\r
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186\r
+#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#################################################################\r
+# Additional Lines to AddOn\r
+#################################################################\r
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
+#all lines are input only\r
+#line 4/5 go to PLL input\r
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 \r
+#################################################################\r
+# Flash ROM and Reboot\r
+#################################################################\r
+LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
+LOCATE COMP "FLASH_CS" SITE "E11" ;\r
+LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
+LOCATE COMP "PROGRAMN" SITE "B11" ;\r
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+#################################################################\r
+# Misc\r
+#################################################################\r
+LOCATE COMP "TEMPSENS" SITE "A13" ;\r
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+#coding of FPGA number\r
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;\r
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;\r
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#terminated differential pair to pads\r
+LOCATE COMP "SUPPL" SITE "C14" ;\r
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
+#################################################################\r
+# LED\r
+#################################################################\r
+LOCATE COMP "LED_GREEN" SITE "F12" ;\r
+LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
+LOCATE COMP "LED_RED" SITE "A15" ;\r
+LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
+DEFINE PORT GROUP "LED_group" "LED*" ;\r
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
+\r
+\r
+#################################################################\r
+#GSR_NET NET "GSR_N"; \r
+#################################################################\r
+# Locate Serdes and media interfaces\r
+#################################################################\r
+LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
+\r
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
+#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
+\r
+BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
+\r
+#UGROUP "SPIlogic" BBOX 20 20\r
+# BLKNAME THE_SPI_RELOAD;\r
+#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
+\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]";\r
+\r
+## IOBUF ALLPORTS ;\r
+USE PRIMARY NET "clk_200_osc" ;\r
+USE PRIMARY NET "clk_100_osc" ;\r
+USE PRIMARY NET "rxup_full_clk" ;\r
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
+FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
jspc29 / soda.git / commitdiff