--- /dev/null
+-- sbuf6: Route through without any registers\r
+\r
+LIBRARY IEEE;\r
+USE IEEE.STD_LOGIC_1164.ALL;\r
+USE IEEE.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+\r
+entity trb_net_sbuf6 is\r
+port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- input\r
+ COMB_DATAREADY_IN : in std_logic;\r
+ COMB_next_READ_OUT : out std_logic;\r
+ COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
+ -- output\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector(18 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG : out std_logic_vector(7 downto 0);\r
+ DEBUG_BSM : out std_logic_vector(3 downto 0);\r
+ DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+);\r
+end entity;\r
+\r
+architecture trb_net_sbuf6_arch of trb_net_sbuf6 is\r
+\r
+begin\r
+\r
+SYN_DATAREADY_OUT <= COMB_DATAREADY_IN;\r
+SYN_DATA_OUT <= COMB_DATA_IN;\r
+COMB_next_READ_OUT <= SYN_READ_IN;\r
+\r
+DEBUG <= (others => '0');\r
+DEBUG_BSM <= (others => '0');\r
+DEBUG_WCNT <= (others => '0');\r
+STAT_BUFFER <= '0';\r
+\r
+end architecture;
\ No newline at end of file