re-add PLL to calibration signal generation

diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
index 3a9ca8d0a393e6f4176e9e9900ee6c6695bb612a..e9d68ed8d1f0bd4c2c725d1a51d1d0b0be338a1a 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
+++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
@@ -93,6 +93,7 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is
   --Clock / Reset
   signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal osc_int                  : std_logic;  -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
   signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
   signal clear_i                  : std_logic;
   signal reset_i                  : std_logic;
@@ -165,6 +166,11 @@ begin
       LOCK  => pll_lock
       );
 
+  pll_calibration : entity work.pll_in125_out33
+    port map (
+      CLK   => CLK_GPLL_LEFT,
+      CLKOP => osc_int,
+      LOCK  => open);
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
@@ -402,7 +408,7 @@ begin
       CLK_READOUT        => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME     => timing_trg_received_i,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_GPLL_LEFT,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => osc_int,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => readout_rx,
       BUSRDO_TX          => readout_tx(0),

diff --git a/releases/tdc_v2.3/trb3_periph_gpin.vhd b/releases/tdc_v2.3/trb3_periph_gpin.vhd
index d6c13b22259f12283d3dcd60856a3d24470b7063..a18d5542e051b2d19f5358a045c14d3584c1f698 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_gpin.vhd
+++ b/releases/tdc_v2.3/trb3_periph_gpin.vhd
@@ -95,6 +95,7 @@ architecture trb3_periph_gpin_arch of trb3_periph_gpin is
   --Clock / Reset
   signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal clk_cal                  : std_logic;  -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
   signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
   signal clear_i                  : std_logic;
   signal reset_i                  : std_logic;
@@ -242,6 +243,11 @@ begin
       LOCK  => pll_lock
       );
 
+  pll_calibration : entity work.pll_in125_out33
+    port map (
+      CLK   => CLK_GPLL_LEFT,
+      CLKOP => clk_cal,
+      LOCK  => open);
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
@@ -656,7 +662,7 @@ begin
       CLK_READOUT        => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME     => timing_trg_received_i,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_GPLL_LEFT,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => readout_rx,
       BUSRDO_TX          => readout_tx(0),

diff --git a/releases/tdc_v2.3/trb3_periph_padiwa.vhd b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
index 569c98e785a8dcecae32503085bd79b6b8837eb4..d02e5010f39ee8417cd5e06c9337018f6d56a15d 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_padiwa.vhd
+++ b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
@@ -104,6 +104,7 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
   --Clock / Reset
   signal clk_100_i                   : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
   signal clk_200_i                   : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal osc_int                     : std_logic;  -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
   signal pll_lock                    : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
   signal clear_i                     : std_logic;
   signal reset_i                     : std_logic;
@@ -267,6 +268,11 @@ begin
       LOCK  => pll_lock
       );
 
+  pll_calibration: entity work.pll_in125_out33
+    port map (
+      CLK   => CLK_GPLL_LEFT,
+      CLKOP => osc_int,
+      LOCK  => open);
 
   gen_sync_clocks : if SYNC_MODE = c_YES generate
     clk_100_i <= rx_clock_100;
@@ -720,7 +726,7 @@ begin
       CLK_READOUT        => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME     => timing_trg_received_i,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_GPLL_LEFT,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => osc_int,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => readout_rx,
       BUSRDO_TX          => readout_tx(0),