*** empty log message ***

diff --git a/cts_fpga1.prj b/cts_fpga1.prj
index 273a9773a508043a6ee63b743405ee79447d0750..1e3f7eb8b88dbf8de7182dd2921cd95909070d10 100644 (file)
--- a/cts_fpga1.prj
+++ b/cts_fpga1.prj
@@ -63,16 +63,22 @@ add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "cts_fpga1.vhd"
 
 #Some of these files have to be regenerated
-# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+
+#Dualported fifo
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
+
+
+#SPI Fifo
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
+
+#Media Interface
+# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
 # add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"
+
+#Collection of fifos for data and trigger handler. fifo_var_oreg is a wrapper around all fifos, lattice_ecp2m_fifo is the library with all component declarations.
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd"
@@ -86,19 +92,7 @@ add_file -vhdl -lib work "cts_fpga1.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
-# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd"
-# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_clock_generator.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-
-
-
+add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd"   #Name has to be kept with scp2m unfortunately.
 
 
 

diff --git a/cts_fpga2.prj b/cts_fpga2.prj
index 35fa2dd5037a7259b755873550ed3e3ab03a4d3c..e9fe3d82a75b106082c9862cd3dda29ae4c2c9dc 100644 (file)
--- a/cts_fpga2.prj
+++ b/cts_fpga2.prj
@@ -69,7 +69,6 @@ add_file -vhdl -lib work "cts_fpga2.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
 # add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"
@@ -87,7 +86,6 @@ add_file -vhdl -lib work "cts_fpga2.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
 # add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd"
 # add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd"